git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@168 c046a42c-6fe2-441c-8c8c-71466251a162
404 lines
11 KiB
C
404 lines
11 KiB
C
/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec-i386.h"
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#include "disas.h"
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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/* main execution loop */
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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void cpu_lock(void)
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{
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spin_lock(&global_cpu_lock);
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}
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void cpu_unlock(void)
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{
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spin_unlock(&global_cpu_lock);
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}
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/* exception support */
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/* NOTE: not static to force relocation generation by GCC */
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void raise_exception_err(int exception_index, int error_code)
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{
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/* NOTE: the register at this point must be saved by hand because
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longjmp restore them */
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#ifdef __sparc__
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/* We have to stay in the same register window as our caller,
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* thus this trick.
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*/
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__asm__ __volatile__("restore\n\t"
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"mov\t%o0, %i0");
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#endif
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#ifdef reg_EAX
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env->regs[R_EAX] = EAX;
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#endif
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#ifdef reg_ECX
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env->regs[R_ECX] = ECX;
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#endif
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#ifdef reg_EDX
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env->regs[R_EDX] = EDX;
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#endif
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#ifdef reg_EBX
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env->regs[R_EBX] = EBX;
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#endif
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#ifdef reg_ESP
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env->regs[R_ESP] = ESP;
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#endif
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#ifdef reg_EBP
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env->regs[R_EBP] = EBP;
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#endif
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#ifdef reg_ESI
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env->regs[R_ESI] = ESI;
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#endif
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#ifdef reg_EDI
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env->regs[R_EDI] = EDI;
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#endif
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env->exception_index = exception_index;
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env->error_code = error_code;
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longjmp(env->jmp_env, 1);
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}
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/* short cut if error_code is 0 or not present */
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void raise_exception(int exception_index)
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{
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raise_exception_err(exception_index, 0);
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}
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int cpu_x86_exec(CPUX86State *env1)
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{
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int saved_T0, saved_T1, saved_A0;
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CPUX86State *saved_env;
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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int code_gen_size, ret, code_size;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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uint8_t *tc_ptr, *cs_base, *pc;
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unsigned int flags;
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/* first we save global registers */
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saved_T0 = T0;
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saved_T1 = T1;
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saved_A0 = A0;
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saved_env = env;
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env = env1;
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#ifdef reg_EAX
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saved_EAX = EAX;
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EAX = env->regs[R_EAX];
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX;
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ECX = env->regs[R_ECX];
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX;
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EDX = env->regs[R_EDX];
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX;
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EBX = env->regs[R_EBX];
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP;
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ESP = env->regs[R_ESP];
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP;
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EBP = env->regs[R_EBP];
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI;
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ESI = env->regs[R_ESI];
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI;
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EDI = env->regs[R_EDI];
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->interrupt_request = 0;
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/* prepare setjmp context for exception handling */
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if (setjmp(env->jmp_env) == 0) {
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for(;;) {
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if (env->interrupt_request) {
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raise_exception(EXCP_INTERRUPT);
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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/* XXX: save all volatile state in cpu state */
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX;
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env->regs[R_EBX] = EBX;
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env->regs[R_ECX] = ECX;
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env->regs[R_EDX] = EDX;
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env->regs[R_ESI] = ESI;
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env->regs[R_EDI] = EDI;
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env->regs[R_EBP] = EBP;
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env->regs[R_ESP] = ESP;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_x86_dump_state(env, logfile, 0);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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}
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
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flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
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flags |= (((unsigned long)env->seg_cache[R_DS].base |
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(unsigned long)env->seg_cache[R_ES].base |
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(unsigned long)env->seg_cache[R_SS].base) != 0) <<
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GEN_FLAG_ADDSEG_SHIFT;
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if (!(env->eflags & VM_MASK)) {
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flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
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} else {
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/* NOTE: a dummy CPL is kept */
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flags |= (1 << GEN_FLAG_VM_SHIFT);
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flags |= (3 << GEN_FLAG_CPL_SHIFT);
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}
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flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
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flags |= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8);
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cs_base = env->seg_cache[R_CS].base;
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pc = cs_base + env->eip;
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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/* if no translated code available, then translate it now */
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/* very inefficient but safe: we lock all the cpus
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when generating code */
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spin_lock(&tb_lock);
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tc_ptr = code_gen_ptr;
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ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
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&code_gen_size, pc, cs_base, flags,
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&code_size);
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/* if invalid instruction, signal it */
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if (ret != 0) {
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP);
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}
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tb = tb_alloc((unsigned long)pc, code_size);
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*ptb = tb;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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tb->tc_ptr = tc_ptr;
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tb->hash_next = NULL;
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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spin_unlock(&tb_lock);
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
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(long)tb->tc_ptr, (long)tb->pc,
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lookup_symbol((void *)tb->pc));
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}
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#endif
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/* execute the generated code */
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tc_ptr = tb->tc_ptr;
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gen_func = (void *)tc_ptr;
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#ifdef __sparc__
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__asm__ __volatile__("call %0\n\t"
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" mov %%o7,%%i0"
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: /* no outputs */
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: "r" (gen_func)
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: "i0", "i1", "i2", "i3", "i4", "i5");
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#else
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gen_func();
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#endif
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}
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}
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ret = env->exception_index;
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/* restore flags in standard format */
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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/* restore global registers */
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#ifdef reg_EAX
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EAX = saved_EAX;
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#endif
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#ifdef reg_ECX
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ECX = saved_ECX;
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#endif
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#ifdef reg_EDX
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EDX = saved_EDX;
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#endif
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#ifdef reg_EBX
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EBX = saved_EBX;
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#endif
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#ifdef reg_ESP
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ESP = saved_ESP;
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#endif
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#ifdef reg_EBP
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EBP = saved_EBP;
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#endif
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#ifdef reg_ESI
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ESI = saved_ESI;
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#endif
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#ifdef reg_EDI
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EDI = saved_EDI;
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#endif
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T0 = saved_T0;
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T1 = saved_T1;
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A0 = saved_A0;
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env = saved_env;
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return ret;
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}
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void cpu_x86_interrupt(CPUX86State *s)
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{
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s->interrupt_request = 1;
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}
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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{
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CPUX86State *saved_env;
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saved_env = env;
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env = s;
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load_seg(seg_reg, selector);
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env = saved_env;
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}
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#include <sys/ucontext.h>
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/* 'pc' is the host PC at which the exception was raised. 'address' is
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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static inline int handle_cpu_signal(unsigned long pc,
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unsigned long address,
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int is_write,
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sigset_t *old_set)
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{
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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pc, address, is_write, *(unsigned long *)old_set);
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#endif
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/* XXX: locking issue */
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if (is_write && page_unprotect(address)) {
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sigprocmask(SIG_SETMASK, old_set, NULL);
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return 1;
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}
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if (pc >= (unsigned long)code_gen_buffer &&
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pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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/* we restore the process signal mask as the sigreturn should
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do it */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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/* XXX: need to compute virtual pc position by retranslating
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code. The rest of the CPU state should be correct. */
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env->cr2 = address;
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raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
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/* never comes here */
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return 1;
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} else {
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return 0;
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}
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}
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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#if defined(__i386__)
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struct ucontext *uc = puc;
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unsigned long pc;
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sigset_t *pold_set;
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#ifndef REG_EIP
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/* for glibc 2.1 */
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#define REG_EIP EIP
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#define REG_ERR ERR
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#define REG_TRAPNO TRAPNO
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#endif
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pc = uc->uc_mcontext.gregs[REG_EIP];
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pold_set = &uc->uc_sigmask;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
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(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
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pold_set);
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#elif defined(__powerpc)
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struct ucontext *uc = puc;
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struct pt_regs *regs = uc->uc_mcontext.regs;
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unsigned long pc;
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sigset_t *pold_set;
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int is_write;
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pc = regs->nip;
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pold_set = &uc->uc_sigmask;
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is_write = 0;
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#if 0
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/* ppc 4xx case */
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if (regs->dsisr & 0x00800000)
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is_write = 1;
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#else
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if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
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is_write = 1;
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#endif
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, pold_set);
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#else
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#error CPU specific signal handler needed
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return 0;
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#endif
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}
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