I/O currently being synchronous, there is no reason to ever clear the SR_TXE bit. However the SR_TC bit may be cleared by software writing to the SR register, so set it on each write. In addition, fix the reset value of the USART status register. Signed-off-by: Richard Braun <rbraun@sceen.net> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> [PMM: removed XXX tag from comment, since it isn't something we need to come back and fix in QEMU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
bcm2835_aux.h | ||
cadence_uart.h | ||
cmsdk-apb-uart.h | ||
digic-uart.h | ||
escc.h | ||
imx_serial.h | ||
lm32_juart.h | ||
pl011.h | ||
serial.h | ||
stm32f2xx_usart.h | ||
xilinx_uartlite.h |