Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlzi6YETHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRNOfD/96OTPguHCDvYtOXqcQ9MpDdbGiMU/U 9UMUietClexHgSIO6mYh4ZF1lApn9UqCqynktNUNQ1HeWhLjc9kka9X9wDSG5VJP kxF4Wt6S6+Re1DBw6KsuHwJTkcrxHnxMDVHEhedjM13bWtnGj0B9SOzGwhN2PVYi +52OWRa/kMa+1M79BG7f49JujFRpDLGRogivrr45XC+kDsP/tSprhZvIO8lF7xpZ MW3i6FdOXQEZKJrVojpQkUU5rm18JojdOBcCY2qvCLpaWfUNW+wNuh1aqT/teUAq ZPOT0NIaq9uBwZ5DNRZxAGVB0MVASYWwMgYoLMcXo8XJdvHUnf9waAs+J4Dl6nfG aiYIWCXENkZ9MDAd672HVb+/gdXp8FDYoazM2+CE4LgPKuGqM+bunVE8OJ/F3rGL iftqx/sb/N09tXFsqINFSaxnkc7kZ1ikQRnonD4CHidcEzyUjJ1X98PAl/vm97yA jpS4OMZXUfNYm5HaGNiDPimhychw2lnHoNUNdlrZ1i6IX5VqSAs8LqDBd3B6ouIr /UKmRyXCgvbU90KC5wdPpPFKvb76SEvfzA+dmGjuP4bhKQvNwcG+zyHpdBaIa4pR 2wrPCICE/07UP5nFLB90SFdfGS/XEJY9RjbGoUY/AOpfdrsASR4QGavI5pmiy71y nK9T0qe/2necVQ== =5Vz/ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging target/xtensa: SR reorganization and options for modern cores Reorganize special register handling to support configurations with conflicting SR definitions. Implement options used by the modern xtensa cores: - memory protection unit; - block prefetch; - exclusive access Add special register definitions and IRQ types for ECC/parity, gather/scatter and IDMA. # gpg: Signature made Mon 20 May 2019 18:53:05 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190520-xtensa: target/xtensa: implement exclusive access option target/xtensa: update list of exception causes target/xtensa: implement block prefetch option opcodes target/xtensa: implement DIWBUI.P opcode target/xtensa: implement MPU option target/xtensa: add parity/ECC option SRs target/xtensa: define IDMA and gather/scatter IRQ types target/xtensa: make internal MMU functions static target/xtensa: get rid of centralized SR properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
212 lines
6.7 KiB
C
212 lines
6.7 KiB
C
/*
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* QEMU Xtensa CPU
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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cpu->env.pc = value;
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}
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static bool xtensa_cpu_has_work(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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XtensaCPU *cpu = XTENSA_CPU(cs);
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return !cpu->env.runstall && cpu->env.pending_irq_level;
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#else
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return true;
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#endif
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}
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/* CPUClass::reset() */
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static void xtensa_cpu_reset(CPUState *s)
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{
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XtensaCPU *cpu = XTENSA_CPU(s);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
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CPUXtensaState *env = &cpu->env;
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xcc->parent_reset(s);
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env->exception_taken = 0;
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env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
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env->sregs[LITBASE] &= ~1;
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#ifndef CONFIG_USER_ONLY
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env->sregs[PS] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
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env->pending_irq_level = 0;
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#else
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env->sregs[PS] =
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(xtensa_option_enabled(env->config,
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XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
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PS_UM | (3 << PS_RING_SHIFT);
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#endif
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env->sregs[VECBASE] = env->config->vecbase;
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env->sregs[IBREAKENABLE] = 0;
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env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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env->sregs[CONFIGID0] = env->config->configid[0];
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env->sregs[CONFIGID1] = env->config->configid[1];
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env->exclusive_addr = -1;
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#ifndef CONFIG_USER_ONLY
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reset_mmu(env);
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s->halted = env->runstall;
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#endif
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}
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static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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info->private_data = cpu->env.config->isa;
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info->print_insn = print_insn_xtensa;
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}
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static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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#ifndef CONFIG_USER_ONLY
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xtensa_irq_init(&XTENSA_CPU(dev)->env);
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#endif
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
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qemu_init_vcpu(cs);
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xcc->parent_realize(dev, errp);
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}
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static void xtensa_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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XtensaCPU *cpu = XTENSA_CPU(obj);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
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CPUXtensaState *env = &cpu->env;
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cs->env_ptr = env;
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env->config = xcc->config;
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#ifndef CONFIG_USER_ONLY
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env->address_space_er = g_malloc(sizeof(*env->address_space_er));
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env->system_er = g_malloc(sizeof(*env->system_er));
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memory_region_init_io(env->system_er, obj, NULL, env, "er",
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UINT64_C(0x100000000));
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address_space_init(env->address_space_er, env->system_er, "ER");
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#endif
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}
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static const VMStateDescription vmstate_xtensa_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
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device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
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&xcc->parent_realize);
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xcc->parent_reset = cc->reset;
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cc->reset = xtensa_cpu_reset;
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cc->class_by_name = xtensa_cpu_class_by_name;
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cc->has_work = xtensa_cpu_has_work;
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cc->do_interrupt = xtensa_cpu_do_interrupt;
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cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
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cc->dump_state = xtensa_cpu_dump_state;
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cc->set_pc = xtensa_cpu_set_pc;
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cc->gdb_read_register = xtensa_cpu_gdb_read_register;
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cc->gdb_write_register = xtensa_cpu_gdb_write_register;
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cc->gdb_stop_before_watchpoint = true;
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cc->tlb_fill = xtensa_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
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cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
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cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
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#endif
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cc->debug_excp_handler = xtensa_breakpoint_handler;
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cc->disas_set_info = xtensa_cpu_disas_set_info;
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cc->tcg_initialize = xtensa_translate_init;
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dc->vmsd = &vmstate_xtensa_cpu;
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}
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static const TypeInfo xtensa_cpu_type_info = {
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.name = TYPE_XTENSA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(XtensaCPU),
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.instance_init = xtensa_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(XtensaCPUClass),
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.class_init = xtensa_cpu_class_init,
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};
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static void xtensa_cpu_register_types(void)
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{
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type_register_static(&xtensa_cpu_type_info);
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}
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type_init(xtensa_cpu_register_types)
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