a4d1f14254
minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2 instructions have been broken when switching target-i386 to softfloat. It's not possible to use comparison instructions on float types anymore to softfloat, so use the floatXX_lt function instead, as the float_XX_min and float_XX_max functions can't be used due to the Intel specific behaviour. As it implements the correct NaNs behaviour, let's remove the corresponding entry from the TODO. It fixes GDM screen display on Debian Lenny. Thanks to Peter Maydell and Jason Wessel for their analysis of the problem. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
32 lines
1 KiB
Plaintext
32 lines
1 KiB
Plaintext
Correctness issues:
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- some eflags manipulation incorrectly reset the bit 0x2.
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- SVM: test, cpu save/restore, SMM save/restore.
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- x86_64: lcall/ljmp intel/amd differences ?
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- better code fetch (different exception handling + CS.limit support)
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- user/kernel PUSHL/POPL in helper.c
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- add missing cpuid tests
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- return UD exception if LOCK prefix incorrectly used
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- test ldt limit < 7 ?
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- fix some 16 bit sp push/pop overflow (pusha/popa, lcall lret)
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- full support of segment limit/rights
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- full x87 exception support
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- improve x87 bit exactness (use bochs code ?)
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- DRx register support
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- CR0.AC emulation
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- SSE alignment checks
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Optimizations/Features:
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- add SVM nested paging support
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- add VMX support
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- add AVX support
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- add SSE5 support
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- fxsave/fxrstor AMD extensions
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- improve monitor/mwait support
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- faster EFLAGS update: consider SZAP, C, O can be updated separately
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with a bit field in CC_OP and more state variables.
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- evaluate x87 stack pointer statically
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- find a way to avoid translating several time the same TB if CR0.TS
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is set or not.
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