284a66a8f6
The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
size occupied by all the registers. However all registers are
32-bit wide, and the MemoryRegionOps handlers are restricted to
32-bit:
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
.read = mchp_pfsoc_mmuart_read,
.write = mchp_pfsoc_mmuart_write,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
Avoid being triskaidekaphobic, simplify by using the number of
registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-2-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* Microchip PolarFire SoC MMUART emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "chardev/char.h"
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#include "hw/char/mchp_pfsoc_mmuart.h"
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static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return 0;
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}
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return s->reg[addr];
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}
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static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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uint32_t val32 = (uint32_t)value;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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" v=0x%x\n", __func__, addr << 2, val32);
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return;
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}
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s->reg[addr] = val32;
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}
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static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
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.read = mchp_pfsoc_mmuart_read,
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.write = mchp_pfsoc_mmuart_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
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hwaddr base, qemu_irq irq, Chardev *chr)
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{
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MchpPfSoCMMUartState *s;
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s = g_new0(MchpPfSoCMMUartState, 1);
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memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
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"mchp.pfsoc.mmuart", 0x1000);
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s->base = base;
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s->irq = irq;
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s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
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DEVICE_LITTLE_ENDIAN);
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memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
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return s;
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}
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