The "ICP" is a different object than the "XICS". For historical reasons, we have a number of places where we name a variable "icp" while it contains a XICSState pointer. There *is* an ICPState structure too so this makes the code really confusing. This is a mechanical replacement of all those instances to use the name "xics" instead. There should be no functional change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [spapr_cpu_init has been moved to spapr_cpu_core.c, change there] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
435 lines
12 KiB
C
435 lines
12 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/xics.h"
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#include "qapi/visitor.h"
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#include "qapi/error.h"
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/*
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* Guest interfaces
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*/
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static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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target_ulong cppr = args[0];
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icp_set_cppr(spapr->xics, cs->cpu_index, cppr);
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return H_SUCCESS;
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}
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static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong server = xics_get_cpu_index_by_dt_id(args[0]);
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target_ulong mfrr = args[1];
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if (server >= spapr->xics->nr_servers) {
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return H_PARAMETER;
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}
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icp_set_mfrr(spapr->xics, server, mfrr);
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return H_SUCCESS;
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}
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static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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uint32_t xirr = icp_accept(spapr->xics->ss + cs->cpu_index);
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args[0] = xirr;
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return H_SUCCESS;
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}
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static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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ICPState *ss = &spapr->xics->ss[cs->cpu_index];
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uint32_t xirr = icp_accept(ss);
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args[0] = xirr;
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args[1] = cpu_get_host_ticks();
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return H_SUCCESS;
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}
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static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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target_ulong xirr = args[0];
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icp_eoi(spapr->xics, cs->cpu_index, xirr);
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return H_SUCCESS;
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}
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static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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uint32_t mfrr;
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uint32_t xirr = icp_ipoll(spapr->xics->ss + cs->cpu_index, &mfrr);
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args[0] = xirr;
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args[1] = mfrr;
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return H_SUCCESS;
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}
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static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->xics->ics;
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uint32_t nr, server, priority;
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if ((nargs != 3) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1));
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priority = rtas_ld(args, 2);
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if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
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|| (priority > 0xff)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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ics_write_xive(ics, nr, server, priority, priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->xics->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 3)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
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rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
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}
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static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->xics->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
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ics->irqs[nr - ics->offset].priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->xics->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
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ics->irqs[nr - ics->offset].saved_priority,
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ics->irqs[nr - ics->offset].saved_priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
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Error **errp)
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{
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xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
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}
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static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
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Error **errp)
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{
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int i;
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xics->nr_servers = nr_servers;
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xics->ss = g_malloc0(xics->nr_servers * sizeof(ICPState));
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for (i = 0; i < xics->nr_servers; i++) {
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char buffer[32];
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object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_ICP);
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snprintf(buffer, sizeof(buffer), "icp[%d]", i);
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object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
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errp);
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}
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}
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static void xics_spapr_realize(DeviceState *dev, Error **errp)
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{
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XICSState *xics = XICS_SPAPR(dev);
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Error *error = NULL;
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int i;
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if (!xics->nr_servers) {
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error_setg(errp, "Number of servers needs to be greater 0");
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return;
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}
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/* Registration of global state belongs into realize */
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spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
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spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
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spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
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spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
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spapr_register_hypercall(H_CPPR, h_cppr);
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spapr_register_hypercall(H_IPI, h_ipi);
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spapr_register_hypercall(H_XIRR, h_xirr);
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spapr_register_hypercall(H_XIRR_X, h_xirr_x);
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spapr_register_hypercall(H_EOI, h_eoi);
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spapr_register_hypercall(H_IPOLL, h_ipoll);
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object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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for (i = 0; i < xics->nr_servers; i++) {
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object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
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&error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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}
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}
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static void xics_spapr_initfn(Object *obj)
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{
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XICSState *xics = XICS_SPAPR(obj);
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xics->ics = ICS(object_new(TYPE_ICS));
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object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
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xics->ics->xics = xics;
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}
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static void xics_spapr_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
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dc->realize = xics_spapr_realize;
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xsc->set_nr_irqs = xics_spapr_set_nr_irqs;
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xsc->set_nr_servers = xics_spapr_set_nr_servers;
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}
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static const TypeInfo xics_spapr_info = {
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.name = TYPE_XICS_SPAPR,
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.parent = TYPE_XICS_COMMON,
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.instance_size = sizeof(XICSState),
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.class_size = sizeof(XICSStateClass),
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.class_init = xics_spapr_class_init,
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.instance_init = xics_spapr_initfn,
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};
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#define ICS_IRQ_FREE(ics, srcno) \
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(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
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static int ics_find_free_block(ICSState *ics, int num, int alignnum)
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{
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int first, i;
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for (first = 0; first < ics->nr_irqs; first += alignnum) {
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if (num > (ics->nr_irqs - first)) {
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return -1;
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}
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for (i = first; i < first + num; ++i) {
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if (!ICS_IRQ_FREE(ics, i)) {
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break;
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}
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}
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if (i == (first + num)) {
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return first;
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}
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}
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return -1;
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}
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int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
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Error **errp)
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{
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ICSState *ics = &xics->ics[src];
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int irq;
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if (irq_hint) {
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assert(src == xics_find_source(xics, irq_hint));
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if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
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error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
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return -1;
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}
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irq = irq_hint;
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} else {
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irq = ics_find_free_block(ics, 1, 1);
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if (irq < 0) {
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error_setg(errp, "can't allocate IRQ: no IRQ left");
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return -1;
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}
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irq += ics->offset;
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}
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ics_set_irq_type(ics, irq - ics->offset, lsi);
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trace_xics_alloc(src, irq);
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return irq;
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}
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/*
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* Allocate block of consecutive IRQs, and return the number of the first IRQ in
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* the block. If align==true, aligns the first IRQ number to num.
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*/
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int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
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bool align, Error **errp)
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{
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int i, first = -1;
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ICSState *ics = &xics->ics[src];
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assert(src == 0);
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/*
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* MSIMesage::data is used for storing VIRQ so
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* it has to be aligned to num to support multiple
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* MSI vectors. MSI-X is not affected by this.
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* The hint is used for the first IRQ, the rest should
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* be allocated continuously.
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*/
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if (align) {
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assert((num == 1) || (num == 2) || (num == 4) ||
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(num == 8) || (num == 16) || (num == 32));
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first = ics_find_free_block(ics, num, num);
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} else {
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first = ics_find_free_block(ics, num, 1);
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}
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if (first < 0) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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if (first >= 0) {
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for (i = first; i < first + num; ++i) {
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ics_set_irq_type(ics, i, lsi);
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}
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}
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first += ics->offset;
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trace_xics_alloc_block(src, first, num, lsi, align);
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return first;
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}
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static void ics_free(ICSState *ics, int srcno, int num)
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{
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int i;
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for (i = srcno; i < srcno + num; ++i) {
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if (ICS_IRQ_FREE(ics, i)) {
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trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
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}
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memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
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}
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}
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void xics_spapr_free(XICSState *xics, int irq, int num)
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{
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int src = xics_find_source(xics, irq);
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if (src >= 0) {
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ICSState *ics = &xics->ics[src];
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/* FIXME: implement multiple sources */
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assert(src == 0);
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trace_xics_ics_free(ics - xics->ics, irq, num);
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ics_free(ics, irq - ics->offset, num);
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}
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}
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static void xics_spapr_register_types(void)
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{
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type_register_static(&xics_spapr_info);
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}
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type_init(xics_spapr_register_types)
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