6a80e088c7
Interrupts are disabled in PALmode, and when the PS IL is high enough. Signed-off-by: Richard Henderson <rth@twiddle.net>
61 lines
2 KiB
C
61 lines
2 KiB
C
/*
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* Alpha emulation cpu run-time definitions for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined (__ALPHA_EXEC_H__)
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#define __ALPHA_EXEC_H__
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#include "config.h"
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#include "dyngen-exec.h"
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#define TARGET_LONG_BITS 64
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register struct CPUAlphaState *env asm(AREG0);
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#define FP_STATUS (env->fp_status)
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#include "cpu.h"
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#include "exec-all.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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static inline int cpu_has_work(CPUState *env)
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{
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/* Here we are checking to see if the CPU should wake up from HALT.
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We will have gotten into this state only for WTINT from PALmode. */
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/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
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asleep even if (some) interrupts have been asserted. For now,
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assume that if a CPU really wants to stay asleep, it will mask
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interrupts at the chipset level, which will prevent these bits
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from being set in the first place. */
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return env->interrupt_request & (CPU_INTERRUPT_HARD
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| CPU_INTERRUPT_TIMER
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| CPU_INTERRUPT_SMP
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| CPU_INTERRUPT_MCHK);
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}
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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}
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#endif /* !defined (__ALPHA_EXEC_H__) */
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