Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-14-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
310 lines
9.4 KiB
C
310 lines
9.4 KiB
C
/*
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* MicroBlaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "exec/log.h"
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#if defined(CONFIG_USER_ONLY)
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bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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cs->exception_index = 0xaa;
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cpu_loop_exit_restore(cs, retaddr);
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}
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#else /* !CONFIG_USER_ONLY */
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static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
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MMUAccessType access_type)
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{
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if (access_type == MMU_INST_FETCH) {
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return !cpu->ns_axi_ip;
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} else {
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return !cpu->ns_axi_dp;
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}
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}
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bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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MicroBlazeMMULookup lu;
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unsigned int hit;
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int prot;
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MemTxAttrs attrs = {};
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attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
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if (mmu_idx == MMU_NOMMU_IDX) {
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/* MMU disabled or not available. */
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address &= TARGET_PAGE_MASK;
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prot = PAGE_BITS;
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tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx,
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TARGET_PAGE_SIZE);
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return true;
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}
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hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
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if (likely(hit)) {
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uint32_t vaddr = address & TARGET_PAGE_MASK;
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uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
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qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
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mmu_idx, vaddr, paddr, lu.prot);
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tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx,
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TARGET_PAGE_SIZE);
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return true;
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}
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/* TLB miss. */
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if (probe) {
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return false;
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}
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qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
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mmu_idx, address);
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env->ear = address;
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switch (lu.err) {
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case ERR_PROT:
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env->esr = access_type == MMU_INST_FETCH ? 17 : 16;
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env->esr |= (access_type == MMU_DATA_STORE) << 10;
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break;
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case ERR_MISS:
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env->esr = access_type == MMU_INST_FETCH ? 19 : 18;
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env->esr |= (access_type == MMU_DATA_STORE) << 10;
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break;
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default:
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abort();
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}
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if (cs->exception_index == EXCP_MMU) {
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cpu_abort(cs, "recursive faults\n");
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}
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/* TLB miss. */
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cs->exception_index = EXCP_MMU;
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cpu_loop_exit_restore(cs, retaddr);
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}
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void mb_cpu_do_interrupt(CPUState *cs)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint32_t t, msr = mb_cpu_read_msr(env);
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bool set_esr;
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/* IMM flag cannot propagate across a branch and into the dslot. */
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assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG));
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/* BIMM flag cannot be set without D_FLAG. */
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assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG);
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/* RTI flags are private to translate. */
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assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
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switch (cs->exception_index) {
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case EXCP_HW_EXCP:
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if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Exception raised on system without exceptions!\n");
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return;
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}
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qemu_log_mask(CPU_LOG_INT,
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"INT: HWE at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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/* Exception breaks branch + dslot sequence? */
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set_esr = true;
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env->esr &= ~D_FLAG;
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if (env->iflags & D_FLAG) {
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env->esr |= D_FLAG;
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env->btr = env->btarget;
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}
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/* Exception in progress. */
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msr |= MSR_EIP;
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env->regs[17] = env->pc + 4;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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case EXCP_MMU:
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qemu_log_mask(CPU_LOG_INT,
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"INT: MMU at pc=%08x msr=%08x "
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"ear=%" PRIx64 " iflags=%x\n",
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env->pc, msr, env->ear, env->iflags);
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/* Exception breaks branch + dslot sequence? */
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set_esr = true;
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env->esr &= ~D_FLAG;
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if (env->iflags & D_FLAG) {
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env->esr |= D_FLAG;
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env->btr = env->btarget;
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/* Reexecute the branch. */
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env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4);
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} else if (env->iflags & IMM_FLAG) {
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/* Reexecute the imm. */
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env->regs[17] = env->pc - 4;
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} else {
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env->regs[17] = env->pc;
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}
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/* Exception in progress. */
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msr |= MSR_EIP;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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case EXCP_IRQ:
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assert(!(msr & (MSR_EIP | MSR_BIP)));
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assert(msr & MSR_IE);
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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qemu_log_mask(CPU_LOG_INT,
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"INT: DEV at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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set_esr = false;
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/* Disable interrupts. */
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msr &= ~MSR_IE;
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env->regs[14] = env->pc;
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env->pc = cpu->cfg.base_vectors + 0x10;
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break;
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case EXCP_HW_BREAK:
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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qemu_log_mask(CPU_LOG_INT,
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"INT: BRK at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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set_esr = false;
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/* Break in progress. */
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msr |= MSR_BIP;
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env->regs[16] = env->pc;
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env->pc = cpu->cfg.base_vectors + 0x18;
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break;
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default:
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cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
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/* not reached */
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}
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/* Save previous mode, disable mmu, disable user-mode. */
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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msr |= t;
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mb_cpu_write_msr(env, msr);
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env->res_addr = RES_ADDR_NONE;
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env->iflags = 0;
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if (!set_esr) {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x\n", env->pc, msr);
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} else if (env->esr & D_FLAG) {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x esr=%04x btr=%08x\n",
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env->pc, msr, env->esr, env->btr);
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} else {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x esr=%04x\n",
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env->pc, msr, env->esr);
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}
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}
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hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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MemTxAttrs *attrs)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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target_ulong vaddr, paddr = 0;
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MicroBlazeMMULookup lu;
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int mmu_idx = cpu_mmu_index(env, false);
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unsigned int hit;
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/* Caller doesn't initialize */
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*attrs = (MemTxAttrs) {};
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attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD);
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if (mmu_idx != MMU_NOMMU_IDX) {
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hit = mmu_translate(cpu, &lu, addr, 0, 0);
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if (hit) {
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vaddr = addr & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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} else
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paddr = 0; /* ???. */
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} else
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paddr = addr & TARGET_PAGE_MASK;
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return paddr;
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}
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bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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if ((interrupt_request & CPU_INTERRUPT_HARD)
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&& (env->msr & MSR_IE)
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&& !(env->msr & (MSR_EIP | MSR_BIP))
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&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
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cs->exception_index = EXCP_IRQ;
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mb_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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uint32_t esr, iflags;
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/* Recover the pc and iflags from the corresponding insn_start. */
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cpu_restore_state(cs, retaddr, true);
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iflags = cpu->env.iflags;
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qemu_log_mask(CPU_LOG_INT,
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"Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n",
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(target_ulong)addr, cpu->env.pc, iflags);
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esr = ESR_EC_UNALIGNED_DATA;
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if (likely(iflags & ESR_ESS_FLAG)) {
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esr |= iflags & ESR_ESS_MASK;
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} else {
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qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
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}
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cpu->env.ear = addr;
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cpu->env.esr = esr;
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cs->exception_index = EXCP_HW_EXCP;
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cpu_loop_exit(cs);
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}
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