This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
410 lines
13 KiB
C
410 lines
13 KiB
C
/*
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* Qemu PowerPC MPC8544DS board emualtion
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "net.h"
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "boards.h"
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#include "sysemu.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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#include "device_tree.h"
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#include "openpic.h"
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#include "ppc.h"
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#include "loader.h"
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#include "elf.h"
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#include "sysbus.h"
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#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
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#define UIMAGE_LOAD_BASE 0
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#define DTC_LOAD_PAD 0x500000
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#define DTC_PAD_MASK 0xFFFFF
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#define INITRD_LOAD_PAD 0x2000000
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#define INITRD_PAD_MASK 0xFFFFFF
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#define RAM_SIZES_ALIGN (64UL << 20)
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#define MPC8544_CCSRBAR_BASE 0xE0000000
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#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
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#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
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#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
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#define MPC8544_PCI_REGS_SIZE 0x1000
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#define MPC8544_PCI_IO 0xE1000000
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#define MPC8544_PCI_IOLEN 0x10000
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#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000)
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#define MPC8544_SPIN_BASE 0xEF000000
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struct boot_info
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{
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uint32_t dt_base;
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uint32_t entry;
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};
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static int mpc8544_load_device_tree(CPUState *env,
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target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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target_phys_addr_t initrd_size,
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const char *kernel_cmdline)
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{
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int ret = -1;
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#ifdef CONFIG_FDT
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uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
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char *filename;
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int fdt_size;
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void *fdt;
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uint8_t hypercall[16];
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uint32_t clock_freq = 400000000;
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uint32_t tb_freq = 400000000;
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int i;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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goto out;
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}
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fdt = load_device_tree(filename, &fdt_size);
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g_free(filename);
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if (fdt == NULL) {
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goto out;
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}
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/* Manipulate device tree in memory. */
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ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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if (ret < 0)
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fprintf(stderr, "couldn't set /memory/reg\n");
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if (initrd_size) {
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0) {
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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}
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0) {
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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}
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}
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ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
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kernel_cmdline);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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if (kvm_enabled()) {
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/* Read out host's frequencies */
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clock_freq = kvmppc_get_clockfreq();
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tb_freq = kvmppc_get_tbfreq();
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/* indicate KVM hypercall interface */
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qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
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"linux,kvm");
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kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
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qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
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hypercall, sizeof(hypercall));
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}
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/* We need to generate the cpu nodes in reverse order, so Linux can pick
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the first node as boot node and be happy */
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for (i = smp_cpus - 1; i >= 0; i--) {
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char cpu_name[128];
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uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
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for (env = first_cpu; env != NULL; env = env->next_cpu) {
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if (env->cpu_index == i) {
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break;
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}
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}
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if (!env) {
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continue;
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}
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snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
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qemu_devtree_add_subnode(fdt, cpu_name);
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qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
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qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
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qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
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qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
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qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
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env->dcache_line_size);
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qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
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env->icache_line_size);
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qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
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qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
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qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
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if (env->cpu_index) {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
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qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
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qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
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&cpu_release_addr, sizeof(cpu_release_addr));
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} else {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
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}
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}
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ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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out:
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#endif
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return ret;
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}
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/* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
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static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
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{
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return ffs(size >> 10) - 1;
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}
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static void mmubooke_create_initial_mapping(CPUState *env,
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target_ulong va,
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target_phys_addr_t pa)
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{
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ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
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target_phys_addr_t size;
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size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT);
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tlb->mas1 = MAS1_VALID | size;
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tlb->mas2 = va & TARGET_PAGE_MASK;
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tlb->mas7_3 = pa & TARGET_PAGE_MASK;
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tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
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env->tlb_dirty = true;
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}
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static void mpc8544ds_cpu_reset_sec(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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/* Secondary CPU starts in halted state for now. Needs to change when
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implementing non-kernel boot. */
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env->halted = 1;
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env->exception_index = EXCP_HLT;
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}
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static void mpc8544ds_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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struct boot_info *bi = env->load_info;
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cpu_reset(env);
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/* Set initial guest state. */
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env->halted = 0;
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env->gpr[1] = (16<<20) - 8;
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env->gpr[3] = bi->dt_base;
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env->nip = bi->entry;
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mmubooke_create_initial_mapping(env, 0, 0);
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}
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static void mpc8544ds_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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PCIBus *pci_bus;
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CPUState *env = NULL;
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uint64_t elf_entry;
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uint64_t elf_lowaddr;
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target_phys_addr_t entry=0;
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target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
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target_long kernel_size=0;
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target_ulong dt_base = 0;
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target_ulong initrd_base = 0;
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target_long initrd_size=0;
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int i=0;
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unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
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qemu_irq **irqs, *mpic;
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DeviceState *dev;
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CPUState *firstenv = NULL;
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/* Setup CPUs */
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if (cpu_model == NULL) {
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cpu_model = "e500v2_v30";
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}
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irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
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irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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for (i = 0; i < smp_cpus; i++) {
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qemu_irq *input;
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env = cpu_ppc_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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if (!firstenv) {
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firstenv = env;
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}
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irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
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input = (qemu_irq *)env->irq_inputs;
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irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
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irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
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env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
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/* XXX register timer? */
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ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR);
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ppc_dcr_init(env, NULL, NULL);
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/* XXX Enable DEC interrupts - probably wrong in the backend */
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env->spr[SPR_40x_TCR] = 1 << 26;
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/* Register reset handler */
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if (!i) {
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/* Primary CPU */
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struct boot_info *boot_info;
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boot_info = g_malloc0(sizeof(struct boot_info));
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qemu_register_reset(mpc8544ds_cpu_reset, env);
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env->load_info = boot_info;
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} else {
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/* Secondary CPUs */
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qemu_register_reset(mpc8544ds_cpu_reset_sec, env);
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}
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}
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env = firstenv;
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/* Fixup Memory size on a alignment boundary */
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ram_size &= ~(RAM_SIZES_ALIGN - 1);
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/* Register Memory */
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cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL,
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"mpc8544ds.ram", ram_size));
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/* MPIC */
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mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL);
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if (!mpic) {
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cpu_abort(env, "MPIC failed to initialize\n");
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}
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/* Serial */
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if (serial_hds[0]) {
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serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
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0, mpic[12+26], 399193,
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serial_hds[0], 1, 1);
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}
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if (serial_hds[1]) {
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serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
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0, mpic[12+26], 399193,
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serial_hds[0], 1, 1);
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}
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/* General Utility device */
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sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
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/* PCI */
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dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
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mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
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mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
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NULL);
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pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pci_bus)
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printf("couldn't create PCI controller!\n");
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isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
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if (pci_bus) {
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/* Register network interfaces. */
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for (i = 0; i < nb_nics; i++) {
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pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
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}
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}
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/* Register spinning region */
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sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
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/* Load kernel. */
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if (kernel_filename) {
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kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
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if (kernel_size < 0) {
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kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
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&elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
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entry = elf_entry;
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loadaddr = elf_lowaddr;
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}
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/* XXX try again as binary */
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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}
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/* Load initrd. */
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if (initrd_filename) {
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initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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/* If we're loading a kernel directly, we must load the device tree too. */
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if (kernel_filename) {
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struct boot_info *boot_info;
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#ifndef CONFIG_FDT
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cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
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#endif
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dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
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if (mpc8544_load_device_tree(env, dt_base, ram_size,
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initrd_base, initrd_size, kernel_cmdline) < 0) {
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fprintf(stderr, "couldn't load device tree\n");
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exit(1);
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}
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boot_info = env->load_info;
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boot_info->entry = entry;
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boot_info->dt_base = dt_base;
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}
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if (kvm_enabled()) {
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kvmppc_init();
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}
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}
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static QEMUMachine mpc8544ds_machine = {
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.name = "mpc8544ds",
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.desc = "mpc8544ds",
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.init = mpc8544ds_init,
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.max_cpus = 15,
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};
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static void mpc8544ds_machine_init(void)
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{
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qemu_register_machine(&mpc8544ds_machine);
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}
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machine_init(mpc8544ds_machine_init);
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