This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. We need a SVE aware compiler as we are testing the id_aa64zfr0_el1 register in the set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200316172155.971-21-alex.bennee@linaro.org>
173 lines
5.7 KiB
C
173 lines
5.7 KiB
C
/*
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* Check emulated system register access for linux-user mode.
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*
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* See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt
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*
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* Copyright (c) 2019 Linaro
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <asm/hwcap.h>
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#include <stdio.h>
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#include <sys/auxv.h>
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#include <signal.h>
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#include <string.h>
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#include <stdbool.h>
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#ifndef HWCAP_CPUID
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#define HWCAP_CPUID (1 << 11)
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#endif
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int failed_bit_count;
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/* Read and print system register `id' value */
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#define get_cpu_reg(id) ({ \
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unsigned long __val = 0xdeadbeef; \
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asm("mrs %0, "#id : "=r" (__val)); \
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printf("%-20s: 0x%016lx\n", #id, __val); \
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__val; \
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})
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/* As above but also check no bits outside of `mask' are set*/
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#define get_cpu_reg_check_mask(id, mask) ({ \
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unsigned long __cval = get_cpu_reg(id); \
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unsigned long __extra = __cval & ~mask; \
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if (__extra) { \
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printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \
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failed_bit_count++; \
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} \
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})
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/* As above but check RAZ */
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#define get_cpu_reg_check_zero(id) ({ \
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unsigned long __val = 0xdeadbeef; \
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asm("mrs %0, "#id : "=r" (__val)); \
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if (__val) { \
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printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \
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failed_bit_count++; \
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} \
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})
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/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */
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#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL)
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bool should_fail;
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int should_fail_count;
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int should_not_fail_count;
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uintptr_t failed_pc[10];
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void sigill_handler(int signo, siginfo_t *si, void *data)
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{
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ucontext_t *uc = (ucontext_t *)data;
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if (should_fail) {
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should_fail_count++;
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} else {
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uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc;
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failed_pc[should_not_fail_count++] = pc;
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}
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uc->uc_mcontext.pc += 4;
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}
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int main(void)
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{
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struct sigaction sa;
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/* Hook in a SIGILL handler */
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memset(&sa, 0, sizeof(struct sigaction));
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sa.sa_flags = SA_SIGINFO;
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sa.sa_sigaction = &sigill_handler;
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sigemptyset(&sa.sa_mask);
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if (sigaction(SIGILL, &sa, 0) != 0) {
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perror("sigaction");
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return 1;
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}
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/* Counter values have been exposed since Linux 4.12 */
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printf("Checking Counter registers\n");
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get_cpu_reg(ctr_el0);
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get_cpu_reg(cntvct_el0);
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get_cpu_reg(cntfrq_el0);
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/* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */
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if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
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printf("CPUID registers unavailable\n");
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return 1;
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} else {
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printf("Checking CPUID registers\n");
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}
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/*
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* Some registers only expose some bits to user-space. Anything
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* that is IMPDEF is exported as 0 to user-space. The _mask checks
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* assert no extra bits are set.
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*
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* This check is *not* comprehensive as some fields are set to
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* minimum valid fields - for the purposes of this check allowed
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* to have non-zero values.
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*/
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get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
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get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
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/* TGran4 & TGran64 as pegged to -1 */
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get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
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get_cpu_reg_check_zero(id_aa64mmfr1_el1);
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/* EL1/EL0 reported as AA64 only */
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get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
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get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
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/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
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get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
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get_cpu_reg_check_zero(id_aa64dfr1_el1);
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get_cpu_reg_check_zero(id_aa64zfr0_el1);
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get_cpu_reg_check_zero(id_aa64afr0_el1);
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get_cpu_reg_check_zero(id_aa64afr1_el1);
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get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff));
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/* mpidr sets bit 31, everything else hidden */
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get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000));
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/* REVIDR is all IMPDEF so should be all zeros to user-space */
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get_cpu_reg_check_zero(revidr_el1);
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/*
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* There are a block of more registers that are RAZ in the rest of
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* the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for
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* brevity we don't check stuff that is currently un-allocated
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* here. Feel free to add them ;-)
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*/
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printf("Remaining registers should fail\n");
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should_fail = true;
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/* Unexposed register access causes SIGILL */
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get_cpu_reg(id_mmfr0_el1);
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get_cpu_reg(id_mmfr1_el1);
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get_cpu_reg(id_mmfr2_el1);
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get_cpu_reg(id_mmfr3_el1);
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get_cpu_reg(mvfr0_el1);
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get_cpu_reg(mvfr1_el1);
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if (should_not_fail_count > 0) {
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int i;
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for (i = 0; i < should_not_fail_count; i++) {
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uintptr_t pc = failed_pc[i];
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uint32_t insn = *(uint32_t *) pc;
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printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc);
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}
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return 1;
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}
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if (failed_bit_count > 0) {
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printf("Extra information leaked to user-space!\n");
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return 1;
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}
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return should_fail_count == 6 ? 0 : 1;
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}
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