All remaining conversions to qdev_realize() are for bus-less devices. Coccinelle script: // only correct for bus-less @dev! @@ expression errp; expression dev; @@ - qdev_init_nofail(dev); + qdev_realize(dev, NULL, &error_fatal); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(OBJECT(dev), true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(dev, true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
203 lines
6.9 KiB
C
203 lines
6.9 KiB
C
/*
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* Allwinner A10 SoC emulation
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*
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* Copyright (C) 2013 Li Guang
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* Written by Li Guang <lig.fnst@cn.fujitsu.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "exec/address-spaces.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/arm/allwinner-a10.h"
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#include "hw/misc/unimp.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/usb/hcd-ohci.h"
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#define AW_A10_MMC0_BASE 0x01c0f000
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#define AW_A10_PIC_REG_BASE 0x01c20400
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#define AW_A10_PIT_REG_BASE 0x01c20c00
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#define AW_A10_UART0_REG_BASE 0x01c28000
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#define AW_A10_EMAC_BASE 0x01c0b000
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#define AW_A10_EHCI_BASE 0x01c14000
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#define AW_A10_OHCI_BASE 0x01c14400
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#define AW_A10_SATA_BASE 0x01c18000
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#define AW_A10_RTC_BASE 0x01c20d00
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static void aw_a10_init(Object *obj)
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{
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AwA10State *s = AW_A10(obj);
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object_initialize_child(obj, "cpu", &s->cpu,
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ARM_CPU_TYPE_NAME("cortex-a8"));
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object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC);
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object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
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object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
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object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
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if (machine_usb(current_machine)) {
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int i;
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for (i = 0; i < AW_A10_NUM_USB; i++) {
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object_initialize_child(obj, "ehci[*]", &s->ehci[i],
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TYPE_PLATFORM_EHCI);
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object_initialize_child(obj, "ohci[*]", &s->ohci[i],
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TYPE_SYSBUS_OHCI);
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}
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}
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object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
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}
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static void aw_a10_realize(DeviceState *dev, Error **errp)
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{
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AwA10State *s = AW_A10(dev);
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SysBusDevice *sysbusdev;
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Error *err = NULL;
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qdev_realize(DEVICE(&s->cpu), NULL, &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbus_realize(SYS_BUS_DEVICE(&s->intc), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->intc);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(sysbusdev, 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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qdev_pass_gpios(DEVICE(&s->intc), dev, NULL);
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sysbus_realize(SYS_BUS_DEVICE(&s->timer), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->timer);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22));
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sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23));
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sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24));
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sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25));
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sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67));
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sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68));
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memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
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&error_fatal);
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memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
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create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
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/* FIXME use qdev NIC properties instead of nd_table[] */
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if (nd_table[0].used) {
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qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->emac);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
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sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55));
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sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56));
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/* FIXME use a qdev chardev prop instead of serial_hd() */
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serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
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qdev_get_gpio_in(dev, 1),
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115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
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if (machine_usb(current_machine)) {
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int i;
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for (i = 0; i < AW_A10_NUM_USB; i++) {
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char bus[16];
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sprintf(bus, "usb-bus.%d", i);
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object_property_set_bool(OBJECT(&s->ehci[i]), true,
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"companion-enable", &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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AW_A10_EHCI_BASE + i * 0x8000);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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qdev_get_gpio_in(dev, 39 + i));
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object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus",
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&error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
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AW_A10_OHCI_BASE + i * 0x8000);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
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qdev_get_gpio_in(dev, 64 + i));
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}
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}
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/* SD/MMC */
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sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
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"sd-bus");
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/* RTC */
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sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
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}
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static void aw_a10_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = aw_a10_realize;
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/* Reason: Uses serial_hds and nd_table in realize function */
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dc->user_creatable = false;
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}
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static const TypeInfo aw_a10_type_info = {
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.name = TYPE_AW_A10,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(AwA10State),
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.instance_init = aw_a10_init,
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.class_init = aw_a10_class_init,
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};
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static void aw_a10_register_types(void)
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{
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type_register_static(&aw_a10_type_info);
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}
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type_init(aw_a10_register_types)
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