Jim Shu 2c2e0f2842 target/riscv: flush TLB pages if PMP permission has been changed ... If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu <cwshu@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-22 21:54:40 -04:00
..
insn_trans	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	Various spelling fixes	2021-03-09 21:19:10 +01:00
cpu.h	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_bits.h	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_helper.c	target/riscv: add log of PMP permission checking	2021-03-22 21:54:40 -04:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: fix vs() to return proper error code	2021-03-22 21:54:40 -04:00
fpu_helper.c	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
gdbstub.c	target/riscv: Generate the GDB XML file for CSR registers dynamically	2021-01-16 10:57:21 -08:00
helper.h	target/riscv: fpu_helper: Match function defs in HELPER macros	2020-12-17 21:56:44 -08:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Add V extension state description	2020-11-03 07:17:23 -08:00
meson.build	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	target/riscv/pmp: Raise exception if no PMP entry is configured	2021-01-16 10:57:21 -08:00
pmp.c	target/riscv: flush TLB pages if PMP permission has been changed	2021-03-22 21:54:40 -04:00
pmp.h	target/riscv: propagate PMP permission to TLB page	2021-03-22 21:54:40 -04:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00