It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
278 lines
7 KiB
C
278 lines
7 KiB
C
/*
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* LatticeMico32 virtual CPU header.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LM32_CPU_H
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#define LM32_CPU_H
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#define TARGET_LONG_BITS 32
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#define CPUArchState struct CPULM32State
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#include "qemu-common.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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struct CPULM32State;
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typedef struct CPULM32State CPULM32State;
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#define NB_MMU_MODES 1
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#define TARGET_PAGE_BITS 12
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static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
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{
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return 0;
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}
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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/* Exceptions indices */
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enum {
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EXCP_RESET = 0,
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EXCP_BREAKPOINT,
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EXCP_INSN_BUS_ERROR,
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EXCP_WATCHPOINT,
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EXCP_DATA_BUS_ERROR,
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EXCP_DIVIDE_BY_ZERO,
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EXCP_IRQ,
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EXCP_SYSTEMCALL
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};
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/* Registers */
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enum {
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R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
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R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
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R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
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R_R31
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};
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/* Register aliases */
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enum {
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R_GP = R_R26,
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R_FP = R_R27,
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R_SP = R_R28,
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R_RA = R_R29,
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R_EA = R_R30,
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R_BA = R_R31
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};
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/* IE flags */
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enum {
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IE_IE = (1<<0),
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IE_EIE = (1<<1),
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IE_BIE = (1<<2),
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};
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/* DC flags */
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enum {
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DC_SS = (1<<0),
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DC_RE = (1<<1),
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DC_C0 = (1<<2),
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DC_C1 = (1<<3),
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DC_C2 = (1<<4),
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DC_C3 = (1<<5),
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};
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/* CFG mask */
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enum {
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CFG_M = (1<<0),
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CFG_D = (1<<1),
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CFG_S = (1<<2),
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CFG_U = (1<<3),
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CFG_X = (1<<4),
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CFG_CC = (1<<5),
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CFG_IC = (1<<6),
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CFG_DC = (1<<7),
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CFG_G = (1<<8),
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CFG_H = (1<<9),
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CFG_R = (1<<10),
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CFG_J = (1<<11),
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CFG_INT_SHIFT = 12,
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CFG_BP_SHIFT = 18,
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CFG_WP_SHIFT = 22,
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CFG_REV_SHIFT = 26,
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};
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/* CSRs */
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enum {
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CSR_IE = 0x00,
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CSR_IM = 0x01,
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CSR_IP = 0x02,
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CSR_ICC = 0x03,
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CSR_DCC = 0x04,
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CSR_CC = 0x05,
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CSR_CFG = 0x06,
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CSR_EBA = 0x07,
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CSR_DC = 0x08,
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CSR_DEBA = 0x09,
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CSR_JTX = 0x0e,
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CSR_JRX = 0x0f,
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CSR_BP0 = 0x10,
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CSR_BP1 = 0x11,
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CSR_BP2 = 0x12,
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CSR_BP3 = 0x13,
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CSR_WP0 = 0x18,
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CSR_WP1 = 0x19,
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CSR_WP2 = 0x1a,
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CSR_WP3 = 0x1b,
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};
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enum {
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LM32_FEATURE_MULTIPLY = 1,
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LM32_FEATURE_DIVIDE = 2,
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LM32_FEATURE_SHIFT = 4,
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LM32_FEATURE_SIGN_EXTEND = 8,
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LM32_FEATURE_I_CACHE = 16,
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LM32_FEATURE_D_CACHE = 32,
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LM32_FEATURE_CYCLE_COUNT = 64,
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};
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enum {
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LM32_FLAG_IGNORE_MSB = 1,
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};
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struct CPULM32State {
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/* general registers */
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uint32_t regs[32];
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/* special registers */
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uint32_t pc; /* program counter */
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uint32_t ie; /* interrupt enable */
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uint32_t icc; /* instruction cache control */
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uint32_t dcc; /* data cache control */
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uint32_t cc; /* cycle counter */
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uint32_t cfg; /* configuration */
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/* debug registers */
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uint32_t dc; /* debug control */
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uint32_t bp[4]; /* breakpoints */
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uint32_t wp[4]; /* watchpoints */
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struct CPUBreakpoint *cpu_breakpoint[4];
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struct CPUWatchpoint *cpu_watchpoint[4];
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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CPU_COMMON
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/* Fields from here on are preserved across CPU reset. */
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uint32_t eba; /* exception base address */
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uint32_t deba; /* debug exception base address */
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/* interrupt controller handle for callbacks */
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DeviceState *pic_state;
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/* JTAG UART handle for callbacks */
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DeviceState *juart_state;
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/* processor core features */
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uint32_t flags;
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};
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/**
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* LM32CPU:
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* @env: #CPULM32State
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*
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* A LatticeMico32 CPU.
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*/
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struct LM32CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPULM32State env;
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uint32_t revision;
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uint8_t num_interrupts;
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uint8_t num_breakpoints;
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uint8_t num_watchpoints;
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uint32_t features;
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};
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static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
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{
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return container_of(env, LM32CPU, env);
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}
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#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
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#define ENV_OFFSET offsetof(LM32CPU, env)
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_lm32_cpu;
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#endif
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void lm32_cpu_do_interrupt(CPUState *cpu);
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bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req);
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void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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typedef enum {
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LM32_WP_DISABLED = 0,
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LM32_WP_READ,
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LM32_WP_WRITE,
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LM32_WP_READ_WRITE,
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} lm32_wp_t;
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static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
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{
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assert(idx < 4);
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return (dc >> (idx+1)*2) & 0x3;
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}
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LM32CPU *cpu_lm32_init(const char *cpu_model);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_lm32_signal_handler(int host_signum, void *pinfo,
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void *puc);
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void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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void lm32_translate_init(void);
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
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void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
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void lm32_debug_excp_handler(CPUState *cs);
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void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
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void lm32_breakpoint_remove(CPULM32State *env, int index);
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void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
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lm32_wp_t wp_type);
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void lm32_watchpoint_remove(CPULM32State *env, int index);
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bool lm32_cpu_do_semihosting(CPUState *cs);
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#define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
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#define cpu_list lm32_cpu_list
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#define cpu_signal_handler cpu_lm32_signal_handler
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int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
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int mmu_idx);
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = 0;
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}
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#endif
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