We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
190 lines
6.2 KiB
C
190 lines
6.2 KiB
C
/*
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* PowerPC emulation special registers manipulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HELPER_REGS_H
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#define HELPER_REGS_H
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/* Swap temporary saved registers with GPRs */
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static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
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{
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target_ulong tmp;
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tmp = env->gpr[0];
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env->gpr[0] = env->tgpr[0];
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env->tgpr[0] = tmp;
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tmp = env->gpr[1];
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env->gpr[1] = env->tgpr[1];
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env->tgpr[1] = tmp;
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tmp = env->gpr[2];
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env->gpr[2] = env->tgpr[2];
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env->tgpr[2] = tmp;
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tmp = env->gpr[3];
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env->gpr[3] = env->tgpr[3];
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env->tgpr[3] = tmp;
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}
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static inline void hreg_compute_mem_idx(CPUPPCState *env)
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{
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/* This is our encoding for server processors. The architecture
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* specifies that there is no such thing as userspace with
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* translation off, however it appears that MacOS does it and
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* some 32-bit CPUs support it. Weird...
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*
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* 0 = Guest User space virtual mode
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* 1 = Guest Kernel space virtual mode
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* 2 = Guest User space real mode
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* 3 = Guest Kernel space real mode
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* 4 = HV User space virtual mode
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* 5 = HV Kernel space virtual mode
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* 6 = HV User space real mode
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* 7 = HV Kernel space real mode
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*
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* For BookE, we need 8 MMU modes as follow:
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*
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* 0 = AS 0 HV User space
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* 1 = AS 0 HV Kernel space
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* 2 = AS 1 HV User space
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* 3 = AS 1 HV Kernel space
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* 4 = AS 0 Guest User space
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* 5 = AS 0 Guest Kernel space
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* 6 = AS 1 Guest User space
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* 7 = AS 1 Guest Kernel space
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*/
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if (env->mmu_model & POWERPC_MMU_BOOKE) {
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env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
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env->immu_idx += msr_is ? 2 : 0;
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env->dmmu_idx += msr_ds ? 2 : 0;
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env->immu_idx += msr_gs ? 4 : 0;
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env->dmmu_idx += msr_gs ? 4 : 0;
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} else {
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env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
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env->immu_idx += msr_ir ? 0 : 2;
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env->dmmu_idx += msr_dr ? 0 : 2;
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env->immu_idx += msr_hv ? 4 : 0;
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env->dmmu_idx += msr_hv ? 4 : 0;
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}
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}
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static inline void hreg_compute_hflags(CPUPPCState *env)
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{
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target_ulong hflags_mask;
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/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
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hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
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(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
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(1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
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hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
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hreg_compute_mem_idx(env);
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env->hflags = env->msr & hflags_mask;
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/* Merge with hflags coming from other registers */
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env->hflags |= env->hflags_nmsr;
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}
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static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
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int alter_hv)
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{
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int excp;
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#if !defined(CONFIG_USER_ONLY)
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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#endif
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excp = 0;
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value &= env->msr_mask;
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#if !defined(CONFIG_USER_ONLY)
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/* Neither mtmsr nor guest state can alter HV */
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if (!alter_hv || !(env->msr & MSR_HVB)) {
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value &= ~MSR_HVB;
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value |= env->msr & MSR_HVB;
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}
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if (((value >> MSR_IR) & 1) != msr_ir ||
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((value >> MSR_DR) & 1) != msr_dr) {
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
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((value >> MSR_GS) & 1) != msr_gs) {
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
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((value ^ env->msr) & (1 << MSR_TGPR)))) {
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/* Swap temporary saved registers with GPRs */
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hreg_swap_gpr_tgpr(env);
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}
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if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
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/* Change the exception prefix on PowerPC 601 */
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env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
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}
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/* If PR=1 then EE, IR and DR must be 1
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*
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* Note: We only enforce this on 64-bit server processors.
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* It appears that:
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* - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
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* exploits it.
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* - 64-bit embedded implementations do not need any operation to be
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* performed when PR is set.
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*/
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if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
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value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
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}
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#endif
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env->msr = value;
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hreg_compute_hflags(env);
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#if !defined(CONFIG_USER_ONLY)
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if (unlikely(msr_pow == 1)) {
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if (!env->pending_interrupts && (*env->check_pow)(env)) {
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cs->halted = 1;
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excp = EXCP_HALTED;
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}
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}
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#endif
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return excp;
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}
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#if !defined(CONFIG_USER_ONLY)
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static inline void check_tlb_flush(CPUPPCState *env, bool global)
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{
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
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tlb_flush(cs);
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env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
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}
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/* Propagate TLB invalidations to other CPUs when the guest uses broadcast
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* TLB invalidation instructions.
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*/
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if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
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CPUState *other_cs;
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CPU_FOREACH(other_cs) {
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if (other_cs != cs) {
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PowerPCCPU *cpu = POWERPC_CPU(other_cs);
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CPUPPCState *other_env = &cpu->env;
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other_env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
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tlb_flush(other_cs);
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}
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}
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env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
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}
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}
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#else
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static inline void check_tlb_flush(CPUPPCState *env, bool global) { }
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#endif
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#endif /* HELPER_REGS_H */
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