We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
210 lines
5.5 KiB
C
210 lines
5.5 KiB
C
/*
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* SPARC gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#ifdef TARGET_ABI32
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#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
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#else
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#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
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#endif
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int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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if (n < 8) {
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/* g0..g7 */
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return gdb_get_rega(mem_buf, env->gregs[n]);
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}
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if (n < 32) {
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/* register window */
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return gdb_get_rega(mem_buf, env->regwptr[n - 8]);
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}
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#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
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if (n < 64) {
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/* fprs */
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if (n & 1) {
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return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
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} else {
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return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
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}
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}
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/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
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switch (n) {
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case 64:
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return gdb_get_rega(mem_buf, env->y);
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case 65:
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return gdb_get_rega(mem_buf, cpu_get_psr(env));
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case 66:
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return gdb_get_rega(mem_buf, env->wim);
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case 67:
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return gdb_get_rega(mem_buf, env->tbr);
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case 68:
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return gdb_get_rega(mem_buf, env->pc);
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case 69:
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return gdb_get_rega(mem_buf, env->npc);
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case 70:
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return gdb_get_rega(mem_buf, env->fsr);
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case 71:
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return gdb_get_rega(mem_buf, 0); /* csr */
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default:
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return gdb_get_rega(mem_buf, 0);
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}
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#else
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if (n < 64) {
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/* f0-f31 */
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if (n & 1) {
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return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);
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} else {
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return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);
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}
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}
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if (n < 80) {
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/* f32-f62 (double width, even numbers only) */
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return gdb_get_reg64(mem_buf, env->fpr[(n - 32) / 2].ll);
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}
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switch (n) {
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case 80:
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return gdb_get_regl(mem_buf, env->pc);
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case 81:
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return gdb_get_regl(mem_buf, env->npc);
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case 82:
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return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |
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((env->asi & 0xff) << 24) |
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((env->pstate & 0xfff) << 8) |
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cpu_get_cwp64(env));
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case 83:
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return gdb_get_regl(mem_buf, env->fsr);
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case 84:
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return gdb_get_regl(mem_buf, env->fprs);
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case 85:
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return gdb_get_regl(mem_buf, env->y);
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}
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#endif
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return 0;
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}
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int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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#if defined(TARGET_ABI32)
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abi_ulong tmp;
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tmp = ldl_p(mem_buf);
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#else
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target_ulong tmp;
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tmp = ldtul_p(mem_buf);
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#endif
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if (n < 8) {
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/* g0..g7 */
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env->gregs[n] = tmp;
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} else if (n < 32) {
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/* register window */
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env->regwptr[n - 8] = tmp;
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}
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#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
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else if (n < 64) {
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/* fprs */
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/* f0-f31 */
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if (n & 1) {
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env->fpr[(n - 32) / 2].l.lower = tmp;
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} else {
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env->fpr[(n - 32) / 2].l.upper = tmp;
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}
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} else {
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/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
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switch (n) {
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case 64:
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env->y = tmp;
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break;
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case 65:
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cpu_put_psr(env, tmp);
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break;
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case 66:
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env->wim = tmp;
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break;
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case 67:
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env->tbr = tmp;
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break;
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case 68:
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env->pc = tmp;
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break;
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case 69:
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env->npc = tmp;
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break;
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case 70:
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env->fsr = tmp;
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break;
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default:
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return 0;
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}
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}
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return 4;
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#else
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else if (n < 64) {
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/* f0-f31 */
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tmp = ldl_p(mem_buf);
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if (n & 1) {
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env->fpr[(n - 32) / 2].l.lower = tmp;
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} else {
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env->fpr[(n - 32) / 2].l.upper = tmp;
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}
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return 4;
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} else if (n < 80) {
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/* f32-f62 (double width, even numbers only) */
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env->fpr[(n - 32) / 2].ll = tmp;
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} else {
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switch (n) {
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case 80:
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env->pc = tmp;
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break;
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case 81:
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env->npc = tmp;
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break;
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case 82:
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cpu_put_ccr(env, tmp >> 32);
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env->asi = (tmp >> 24) & 0xff;
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env->pstate = (tmp >> 8) & 0xfff;
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cpu_put_cwp64(env, tmp & 0xff);
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break;
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case 83:
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env->fsr = tmp;
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break;
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case 84:
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env->fprs = tmp;
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break;
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case 85:
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env->y = tmp;
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break;
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default:
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return 0;
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}
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}
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return 8;
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#endif
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}
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