We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
147 lines
4.2 KiB
C
147 lines
4.2 KiB
C
/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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};
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#if defined(CONFIG_SOFTMMU)
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static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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int ret = TLBRET_MATCH;
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return ret;
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}
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#endif
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/* TODO: Add exeption support*/
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static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
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int rw, int tlb_error)
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{
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}
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int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
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int rw, int mmu_idx)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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hwaddr physical;
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int prot;
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int access_type;
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int ret = 0;
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rw &= 1;
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access_type = ACCESS_INT;
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type);
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qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
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" prot %d\n", __func__, address, ret, physical, prot);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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} else if (ret < 0) {
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raise_mmu_exception(env, address, rw, ret);
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ret = 1;
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}
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return ret;
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}
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TriCoreCPU *cpu_tricore_init(const char *cpu_model)
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{
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return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model));
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}
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static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CPUListState *s = user_data;
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const char *typename;
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char *name;
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typename = object_class_get_name(oc);
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
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(*s->cpu_fprintf)(s->file, " %s\n",
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name);
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g_free(name);
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}
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void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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CPUListState s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_TRICORE_CPU, false);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, tricore_cpu_list_entry, &s);
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g_slist_free(list);
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}
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void fpu_set_state(CPUTriCoreState *env)
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{
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set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
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set_flush_inputs_to_zero(1, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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set_default_nan_mode(1, &env->fp_status);
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}
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uint32_t psw_read(CPUTriCoreState *env)
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{
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/* clear all USB bits */
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env->PSW &= 0x6ffffff;
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/* now set them from the cache */
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env->PSW |= ((env->PSW_USB_C != 0) << 31);
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env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
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env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2);
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env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3);
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env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4);
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return env->PSW;
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}
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void psw_write(CPUTriCoreState *env, uint32_t val)
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{
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env->PSW_USB_C = (val & MASK_USB_C);
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env->PSW_USB_V = (val & MASK_USB_V) << 1;
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env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
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env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
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env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
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env->PSW = val;
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fpu_set_state(env);
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}
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