Since 39bffca203
(qdev: register all
types natively through QEMU Object Model), TypeInfo as used in
the common, non-iterative pattern is no longer amended with information
and should therefore be const.
Fix the documented QOM examples:
sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h
Since frequently the wrong examples are being copied by contributors of
new devices, fix all types in the tree:
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c
sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c
This also avoids to piggy-back these changes onto real functional
changes or other refactorings.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
450 lines
13 KiB
C
450 lines
13 KiB
C
/*
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* Luminary Micro Stellaris Ethernet Controller
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "net/net.h"
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#include <zlib.h>
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//#define DEBUG_STELLARIS_ENET 1
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#ifdef DEBUG_STELLARIS_ENET
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#define DPRINTF(fmt, ...) \
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do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
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#endif
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#define SE_INT_RX 0x01
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#define SE_INT_TXER 0x02
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#define SE_INT_TXEMP 0x04
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#define SE_INT_FOV 0x08
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#define SE_INT_RXER 0x10
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#define SE_INT_MD 0x20
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#define SE_INT_PHY 0x40
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#define SE_RCTL_RXEN 0x01
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#define SE_RCTL_AMUL 0x02
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#define SE_RCTL_PRMS 0x04
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#define SE_RCTL_BADCRC 0x08
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#define SE_RCTL_RSTFIFO 0x10
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#define SE_TCTL_TXEN 0x01
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#define SE_TCTL_PADEN 0x02
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#define SE_TCTL_CRC 0x04
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#define SE_TCTL_DUPLEX 0x08
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typedef struct {
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SysBusDevice busdev;
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uint32_t ris;
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uint32_t im;
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uint32_t rctl;
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uint32_t tctl;
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uint32_t thr;
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uint32_t mctl;
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uint32_t mdv;
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uint32_t mtxd;
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uint32_t mrxd;
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uint32_t np;
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int tx_frame_len;
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int tx_fifo_len;
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uint8_t tx_fifo[2048];
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/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
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We implement a full 31 packet fifo. */
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struct {
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uint8_t data[2048];
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int len;
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} rx[31];
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uint8_t *rx_fifo;
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int rx_fifo_len;
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int next_packet;
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NICState *nic;
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NICConf conf;
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qemu_irq irq;
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MemoryRegion mmio;
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} stellaris_enet_state;
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static void stellaris_enet_update(stellaris_enet_state *s)
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{
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qemu_set_irq(s->irq, (s->ris & s->im) != 0);
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}
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/* TODO: Implement MAC address filtering. */
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static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
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int n;
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uint8_t *p;
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uint32_t crc;
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if ((s->rctl & SE_RCTL_RXEN) == 0)
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return -1;
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if (s->np >= 31) {
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DPRINTF("Packet dropped\n");
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return -1;
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}
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DPRINTF("Received packet len=%d\n", size);
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n = s->next_packet + s->np;
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if (n >= 31)
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n -= 31;
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s->np++;
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s->rx[n].len = size + 6;
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p = s->rx[n].data;
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*(p++) = (size + 6);
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*(p++) = (size + 6) >> 8;
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memcpy (p, buf, size);
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p += size;
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crc = crc32(~0, buf, size);
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*(p++) = crc;
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*(p++) = crc >> 8;
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*(p++) = crc >> 16;
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*(p++) = crc >> 24;
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/* Clear the remaining bytes in the last word. */
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if ((size & 3) != 2) {
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memset(p, 0, (6 - size) & 3);
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}
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s->ris |= SE_INT_RX;
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stellaris_enet_update(s);
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return size;
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}
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static int stellaris_enet_can_receive(NetClientState *nc)
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{
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stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
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if ((s->rctl & SE_RCTL_RXEN) == 0)
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return 1;
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return (s->np < 31);
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}
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static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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uint32_t val;
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switch (offset) {
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case 0x00: /* RIS */
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DPRINTF("IRQ status %02x\n", s->ris);
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return s->ris;
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case 0x04: /* IM */
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return s->im;
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case 0x08: /* RCTL */
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return s->rctl;
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case 0x0c: /* TCTL */
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return s->tctl;
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case 0x10: /* DATA */
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if (s->rx_fifo_len == 0) {
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if (s->np == 0) {
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BADF("RX underflow\n");
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return 0;
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}
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s->rx_fifo_len = s->rx[s->next_packet].len;
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s->rx_fifo = s->rx[s->next_packet].data;
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DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
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}
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val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
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| (s->rx_fifo[3] << 24);
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s->rx_fifo += 4;
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s->rx_fifo_len -= 4;
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if (s->rx_fifo_len <= 0) {
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s->rx_fifo_len = 0;
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s->next_packet++;
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if (s->next_packet >= 31)
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s->next_packet = 0;
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s->np--;
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DPRINTF("RX done np=%d\n", s->np);
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}
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return val;
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case 0x14: /* IA0 */
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return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
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| (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
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case 0x18: /* IA1 */
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return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
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case 0x1c: /* THR */
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return s->thr;
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case 0x20: /* MCTL */
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return s->mctl;
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case 0x24: /* MDV */
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return s->mdv;
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case 0x28: /* MADD */
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return 0;
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case 0x2c: /* MTXD */
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return s->mtxd;
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case 0x30: /* MRXD */
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return s->mrxd;
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case 0x34: /* NP */
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return s->np;
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case 0x38: /* TR */
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return 0;
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case 0x3c: /* Undocuented: Timestamp? */
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return 0;
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default:
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hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void stellaris_enet_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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switch (offset) {
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case 0x00: /* IACK */
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s->ris &= ~value;
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DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
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stellaris_enet_update(s);
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/* Clearing TXER also resets the TX fifo. */
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if (value & SE_INT_TXER)
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s->tx_frame_len = -1;
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break;
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case 0x04: /* IM */
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DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
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s->im = value;
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stellaris_enet_update(s);
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break;
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case 0x08: /* RCTL */
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s->rctl = value;
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if (value & SE_RCTL_RSTFIFO) {
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s->rx_fifo_len = 0;
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s->np = 0;
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stellaris_enet_update(s);
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}
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break;
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case 0x0c: /* TCTL */
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s->tctl = value;
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break;
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case 0x10: /* DATA */
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if (s->tx_frame_len == -1) {
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s->tx_frame_len = value & 0xffff;
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if (s->tx_frame_len > 2032) {
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DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
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s->tx_frame_len = 0;
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s->ris |= SE_INT_TXER;
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stellaris_enet_update(s);
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} else {
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DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
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/* The value written does not include the ethernet header. */
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s->tx_frame_len += 14;
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if ((s->tctl & SE_TCTL_CRC) == 0)
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s->tx_frame_len += 4;
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s->tx_fifo_len = 0;
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s->tx_fifo[s->tx_fifo_len++] = value >> 16;
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s->tx_fifo[s->tx_fifo_len++] = value >> 24;
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}
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} else {
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s->tx_fifo[s->tx_fifo_len++] = value;
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s->tx_fifo[s->tx_fifo_len++] = value >> 8;
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s->tx_fifo[s->tx_fifo_len++] = value >> 16;
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s->tx_fifo[s->tx_fifo_len++] = value >> 24;
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if (s->tx_fifo_len >= s->tx_frame_len) {
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/* We don't implement explicit CRC, so just chop it off. */
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if ((s->tctl & SE_TCTL_CRC) == 0)
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s->tx_frame_len -= 4;
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if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
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memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
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s->tx_fifo_len = 60;
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}
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qemu_send_packet(&s->nic->nc, s->tx_fifo, s->tx_frame_len);
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s->tx_frame_len = -1;
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s->ris |= SE_INT_TXEMP;
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stellaris_enet_update(s);
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DPRINTF("Done TX\n");
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}
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}
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break;
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case 0x14: /* IA0 */
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s->conf.macaddr.a[0] = value;
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s->conf.macaddr.a[1] = value >> 8;
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s->conf.macaddr.a[2] = value >> 16;
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s->conf.macaddr.a[3] = value >> 24;
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break;
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case 0x18: /* IA1 */
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s->conf.macaddr.a[4] = value;
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s->conf.macaddr.a[5] = value >> 8;
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break;
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case 0x1c: /* THR */
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s->thr = value;
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break;
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case 0x20: /* MCTL */
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s->mctl = value;
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break;
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case 0x24: /* MDV */
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s->mdv = value;
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break;
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case 0x28: /* MADD */
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/* ignored. */
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break;
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case 0x2c: /* MTXD */
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s->mtxd = value & 0xff;
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break;
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case 0x30: /* MRXD */
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case 0x34: /* NP */
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case 0x38: /* TR */
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/* Ignored. */
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case 0x3c: /* Undocuented: Timestamp? */
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/* Ignored. */
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break;
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default:
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hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps stellaris_enet_ops = {
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.read = stellaris_enet_read,
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.write = stellaris_enet_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stellaris_enet_reset(stellaris_enet_state *s)
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{
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s->mdv = 0x80;
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s->rctl = SE_RCTL_BADCRC;
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s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
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| SE_INT_TXER | SE_INT_RX;
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s->thr = 0x3f;
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s->tx_frame_len = -1;
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}
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static void stellaris_enet_save(QEMUFile *f, void *opaque)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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int i;
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qemu_put_be32(f, s->ris);
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qemu_put_be32(f, s->im);
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qemu_put_be32(f, s->rctl);
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qemu_put_be32(f, s->tctl);
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qemu_put_be32(f, s->thr);
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qemu_put_be32(f, s->mctl);
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qemu_put_be32(f, s->mdv);
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qemu_put_be32(f, s->mtxd);
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qemu_put_be32(f, s->mrxd);
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qemu_put_be32(f, s->np);
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qemu_put_be32(f, s->tx_frame_len);
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qemu_put_be32(f, s->tx_fifo_len);
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qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
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for (i = 0; i < 31; i++) {
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qemu_put_be32(f, s->rx[i].len);
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qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
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}
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qemu_put_be32(f, s->next_packet);
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qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
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qemu_put_be32(f, s->rx_fifo_len);
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}
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static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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s->ris = qemu_get_be32(f);
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s->im = qemu_get_be32(f);
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s->rctl = qemu_get_be32(f);
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s->tctl = qemu_get_be32(f);
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s->thr = qemu_get_be32(f);
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s->mctl = qemu_get_be32(f);
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s->mdv = qemu_get_be32(f);
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s->mtxd = qemu_get_be32(f);
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s->mrxd = qemu_get_be32(f);
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s->np = qemu_get_be32(f);
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s->tx_frame_len = qemu_get_be32(f);
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s->tx_fifo_len = qemu_get_be32(f);
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qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
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for (i = 0; i < 31; i++) {
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s->rx[i].len = qemu_get_be32(f);
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qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
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}
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s->next_packet = qemu_get_be32(f);
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s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
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s->rx_fifo_len = qemu_get_be32(f);
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return 0;
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}
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static void stellaris_enet_cleanup(NetClientState *nc)
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{
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stellaris_enet_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
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unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
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memory_region_destroy(&s->mmio);
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g_free(s);
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}
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static NetClientInfo net_stellaris_enet_info = {
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.type = NET_CLIENT_OPTIONS_KIND_NIC,
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.size = sizeof(NICState),
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.can_receive = stellaris_enet_can_receive,
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.receive = stellaris_enet_receive,
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.cleanup = stellaris_enet_cleanup,
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};
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static int stellaris_enet_init(SysBusDevice *dev)
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{
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stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
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memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
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0x1000);
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sysbus_init_mmio(dev, &s->mmio);
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sysbus_init_irq(dev, &s->irq);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
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object_get_typename(OBJECT(dev)), dev->qdev.id, s);
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qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
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stellaris_enet_reset(s);
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register_savevm(&s->busdev.qdev, "stellaris_enet", -1, 1,
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stellaris_enet_save, stellaris_enet_load, s);
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return 0;
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}
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static Property stellaris_enet_properties[] = {
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DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stellaris_enet_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = stellaris_enet_init;
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dc->props = stellaris_enet_properties;
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}
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static const TypeInfo stellaris_enet_info = {
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.name = "stellaris_enet",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(stellaris_enet_state),
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.class_init = stellaris_enet_class_init,
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};
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static void stellaris_enet_register_types(void)
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{
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type_register_static(&stellaris_enet_info);
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}
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type_init(stellaris_enet_register_types)
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