Patch 5/7 This patch changes the graphical_console_init function to return an allocated DisplayState instead of a QEMUConsole. This patch contains just the graphical_console_init change and few other modifications mainly in console.c and vl.c. It was necessary to move the display frontends (e.g. sdl and vnc) initialization after machine->init in vl.c. This patch does *not* include any required changes to any device, these changes come with the following patches. Patch 6/7 This patch changes the QEMUMachine init functions not to take a DisplayState as an argument because is not needed any more; In few places the graphic hardware initialization function was called only if DisplayState was not NULL, now they are always called. Apart from these cases, the rest are all mechanical substitutions. Patch 7/7 This patch updates the graphic device code to use the new graphical_console_init function. As for the previous patch, in few places graphical_console_init was called only if DisplayState was not NULL, now it is always called. Apart from these cases, the rest are all mechanical substitutions. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6344 c046a42c-6fe2-441c-8c8c-71466251a162
429 lines
10 KiB
C
429 lines
10 KiB
C
/*
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* Arm PrimeCell PL110 Color LCD Controller
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GNU LGPL
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*/
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#include "hw.h"
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#include "primecell.h"
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#include "console.h"
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#define PL110_CR_EN 0x001
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#define PL110_CR_BGR 0x100
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#define PL110_CR_BEBO 0x200
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#define PL110_CR_BEPO 0x400
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#define PL110_CR_PWR 0x800
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enum pl110_bppmode
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{
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BPP_1,
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BPP_2,
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BPP_4,
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BPP_8,
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BPP_16,
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BPP_32
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};
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typedef struct {
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DisplayState *ds;
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/* The Versatile/PB uses a slightly modified PL110 controller. */
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int versatile;
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uint32_t timing[4];
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uint32_t cr;
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uint32_t upbase;
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uint32_t lpbase;
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uint32_t int_status;
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uint32_t int_mask;
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int cols;
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int rows;
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enum pl110_bppmode bpp;
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int invalidate;
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uint32_t pallette[256];
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uint32_t raw_pallette[128];
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qemu_irq irq;
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} pl110_state;
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static const unsigned char pl110_id[] =
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{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
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has a different ID. However Linux only looks for the normal ID. */
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#if 0
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static const unsigned char pl110_versatile_id[] =
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{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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#else
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#define pl110_versatile_id pl110_id
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#endif
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static inline uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
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{
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return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
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}
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static inline uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
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{
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return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
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}
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static inline uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
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{
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return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
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}
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static inline uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
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{
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return (r << 16) | (g << 8) | b;
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}
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static inline uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
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{
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return (r << 16) | (g << 8) | b;
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}
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typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);
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#define BITS 8
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#include "pl110_template.h"
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#define BITS 15
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#include "pl110_template.h"
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#define BITS 16
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#include "pl110_template.h"
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#define BITS 24
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#include "pl110_template.h"
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#define BITS 32
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#include "pl110_template.h"
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static int pl110_enabled(pl110_state *s)
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{
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return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
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}
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static void pl110_update_display(void *opaque)
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{
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pl110_state *s = (pl110_state *)opaque;
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drawfn* fntable;
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drawfn fn;
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uint32_t *pallette;
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uint32_t addr;
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uint32_t base;
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int dest_width;
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int src_width;
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uint8_t *dest;
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uint8_t *src;
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int first, last = 0;
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int dirty, new_dirty;
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int i;
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int bpp_offset;
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if (!pl110_enabled(s))
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return;
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 0:
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return;
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case 8:
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fntable = pl110_draw_fn_8;
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dest_width = 1;
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break;
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case 15:
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fntable = pl110_draw_fn_15;
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dest_width = 2;
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break;
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case 16:
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fntable = pl110_draw_fn_16;
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dest_width = 2;
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break;
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case 24:
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fntable = pl110_draw_fn_24;
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dest_width = 3;
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break;
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case 32:
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fntable = pl110_draw_fn_32;
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dest_width = 4;
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break;
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default:
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fprintf(stderr, "pl110: Bad color depth\n");
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exit(1);
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}
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if (s->cr & PL110_CR_BGR)
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bpp_offset = 0;
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else
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bpp_offset = 18;
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if (s->cr & PL110_CR_BEBO)
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fn = fntable[s->bpp + 6 + bpp_offset];
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else if (s->cr & PL110_CR_BEPO)
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fn = fntable[s->bpp + 12 + bpp_offset];
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else
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fn = fntable[s->bpp + bpp_offset];
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src_width = s->cols;
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switch (s->bpp) {
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case BPP_1:
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src_width >>= 3;
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break;
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case BPP_2:
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src_width >>= 2;
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break;
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case BPP_4:
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src_width >>= 1;
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break;
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case BPP_8:
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break;
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case BPP_16:
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src_width <<= 1;
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break;
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case BPP_32:
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src_width <<= 2;
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break;
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}
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dest_width *= s->cols;
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pallette = s->pallette;
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base = s->upbase;
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/* HACK: Arm aliases physical memory at 0x80000000. */
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if (base > 0x80000000)
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base -= 0x80000000;
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src = phys_ram_base + base;
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dest = ds_get_data(s->ds);
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first = -1;
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addr = base;
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dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
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new_dirty = dirty;
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for (i = 0; i < s->rows; i++) {
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if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
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uint32_t tmp;
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new_dirty = 0;
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for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
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new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
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VGA_DIRTY_FLAG);
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}
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}
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if (dirty || new_dirty || s->invalidate) {
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fn(pallette, dest, src, s->cols);
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if (first == -1)
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first = i;
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last = i;
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}
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dirty = new_dirty;
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addr += src_width;
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dest += dest_width;
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src += src_width;
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}
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if (first < 0)
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return;
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s->invalidate = 0;
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cpu_physical_memory_reset_dirty(base + first * src_width,
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base + (last + 1) * src_width,
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VGA_DIRTY_FLAG);
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dpy_update(s->ds, 0, first, s->cols, last - first + 1);
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}
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static void pl110_invalidate_display(void * opaque)
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{
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pl110_state *s = (pl110_state *)opaque;
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s->invalidate = 1;
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}
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static void pl110_update_pallette(pl110_state *s, int n)
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{
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int i;
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uint32_t raw;
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unsigned int r, g, b;
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raw = s->raw_pallette[n];
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n <<= 1;
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for (i = 0; i < 2; i++) {
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r = (raw & 0x1f) << 3;
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raw >>= 5;
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g = (raw & 0x1f) << 3;
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raw >>= 5;
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b = (raw & 0x1f) << 3;
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/* The I bit is ignored. */
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raw >>= 6;
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 8:
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s->pallette[n] = rgb_to_pixel8(r, g, b);
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break;
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case 15:
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s->pallette[n] = rgb_to_pixel15(r, g, b);
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break;
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case 16:
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s->pallette[n] = rgb_to_pixel16(r, g, b);
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break;
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case 24:
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case 32:
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s->pallette[n] = rgb_to_pixel32(r, g, b);
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break;
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}
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n++;
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}
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}
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static void pl110_resize(pl110_state *s, int width, int height)
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{
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if (width != s->cols || height != s->rows) {
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if (pl110_enabled(s)) {
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qemu_console_resize(s->ds, width, height);
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}
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}
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s->cols = width;
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s->rows = height;
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}
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/* Update interrupts. */
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static void pl110_update(pl110_state *s)
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{
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/* TODO: Implement interrupts. */
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}
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static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
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{
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pl110_state *s = (pl110_state *)opaque;
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if (offset >= 0xfe0 && offset < 0x1000) {
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if (s->versatile)
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return pl110_versatile_id[(offset - 0xfe0) >> 2];
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else
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return pl110_id[(offset - 0xfe0) >> 2];
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}
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if (offset >= 0x200 && offset < 0x400) {
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return s->raw_pallette[(offset - 0x200) >> 2];
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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return s->timing[0];
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case 1: /* LCDTiming1 */
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return s->timing[1];
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case 2: /* LCDTiming2 */
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return s->timing[2];
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case 3: /* LCDTiming3 */
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return s->timing[3];
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case 4: /* LCDUPBASE */
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return s->upbase;
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case 5: /* LCDLPBASE */
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return s->lpbase;
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case 6: /* LCDIMSC */
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if (s->versatile)
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return s->cr;
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return s->int_mask;
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case 7: /* LCDControl */
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if (s->versatile)
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return s->int_mask;
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return s->cr;
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case 8: /* LCDRIS */
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return s->int_status;
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case 9: /* LCDMIS */
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return s->int_status & s->int_mask;
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case 11: /* LCDUPCURR */
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/* TODO: Implement vertical refresh. */
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return s->upbase;
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case 12: /* LCDLPCURR */
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return s->lpbase;
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default:
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cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl110_write(void *opaque, target_phys_addr_t offset,
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uint32_t val)
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{
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pl110_state *s = (pl110_state *)opaque;
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int n;
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/* For simplicity invalidate the display whenever a control register
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is writen to. */
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s->invalidate = 1;
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if (offset >= 0x200 && offset < 0x400) {
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/* Pallette. */
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n = (offset - 0x200) >> 2;
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s->raw_pallette[(offset - 0x200) >> 2] = val;
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pl110_update_pallette(s, n);
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return;
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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s->timing[0] = val;
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n = ((val & 0xfc) + 4) * 4;
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pl110_resize(s, n, s->rows);
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break;
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case 1: /* LCDTiming1 */
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s->timing[1] = val;
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n = (val & 0x3ff) + 1;
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pl110_resize(s, s->cols, n);
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break;
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case 2: /* LCDTiming2 */
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s->timing[2] = val;
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break;
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case 3: /* LCDTiming3 */
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s->timing[3] = val;
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break;
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case 4: /* LCDUPBASE */
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s->upbase = val;
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break;
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case 5: /* LCDLPBASE */
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s->lpbase = val;
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break;
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case 6: /* LCDIMSC */
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if (s->versatile)
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goto control;
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imsc:
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s->int_mask = val;
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pl110_update(s);
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break;
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case 7: /* LCDControl */
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if (s->versatile)
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goto imsc;
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control:
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s->cr = val;
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s->bpp = (val >> 1) & 7;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->ds, s->cols, s->rows);
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}
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break;
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case 10: /* LCDICR */
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s->int_status &= ~val;
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pl110_update(s);
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break;
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default:
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cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
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}
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}
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static CPUReadMemoryFunc *pl110_readfn[] = {
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pl110_read,
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pl110_read,
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pl110_read
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};
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static CPUWriteMemoryFunc *pl110_writefn[] = {
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pl110_write,
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pl110_write,
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pl110_write
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};
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void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
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{
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pl110_state *s;
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int iomemtype;
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s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
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iomemtype = cpu_register_io_memory(0, pl110_readfn,
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pl110_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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s->versatile = versatile;
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s->irq = irq;
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s->ds = graphic_console_init(pl110_update_display,
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pl110_invalidate_display,
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NULL, NULL, s);
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/* ??? Save/restore. */
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return s;
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}
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