a26fc6f515
Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <2a10a1f1c00a894af1212c8f68ef09c2966023c1.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
72 lines
2.6 KiB
C
72 lines
2.6 KiB
C
/*
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* Memory transaction attributes
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*
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* Copyright (c) 2015 Linaro Limited.
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*
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* Authors:
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* Peter Maydell <peter.maydell@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef MEMATTRS_H
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#define MEMATTRS_H
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/* Every memory transaction has associated with it a set of
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* attributes. Some of these are generic (such as the ID of
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* the bus master); some are specific to a particular kind of
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* bus (such as the ARM Secure/NonSecure bit). We define them
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* all as non-overlapping bitfields in a single struct to avoid
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* confusion if different parts of QEMU used the same bit for
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* different semantics.
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*/
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typedef struct MemTxAttrs {
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/* Bus masters which don't specify any attributes will get this
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* (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
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* distinguish "all attributes deliberately clear" from
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* "didn't specify" if necessary.
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*/
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unsigned int unspecified:1;
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/* ARM/AMBA: TrustZone Secure access
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* x86: System Management Mode access
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*/
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unsigned int secure:1;
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/* Memory access is usermode (unprivileged) */
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unsigned int user:1;
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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/* Invert endianness for this page */
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unsigned int byte_swap:1;
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/*
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* The following are target-specific page-table bits. These are not
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* related to actual memory transactions at all. However, this structure
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* is part of the tlb_fill interface, cached in the cputlb structure,
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* and has unused bits. These fields will be read by target-specific
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* helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
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*/
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unsigned int target_tlb_bit0 : 1;
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unsigned int target_tlb_bit1 : 1;
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unsigned int target_tlb_bit2 : 1;
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} MemTxAttrs;
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/* Bus masters which don't specify any attributes will get this,
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* which has all attribute bits clear except the topmost one
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* (so that we can distinguish "all attributes deliberately clear"
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* from "didn't specify" if necessary).
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*/
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#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
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/* New-style MMIO accessors can indicate that the transaction failed.
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* A zero (MEMTX_OK) response means success; anything else is a failure
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* of some kind. The memory subsystem will bitwise-OR together results
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* if it is synthesizing an operation from multiple smaller accesses.
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*/
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#define MEMTX_OK 0
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#define MEMTX_ERROR (1U << 0) /* device returned an error */
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#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
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typedef uint32_t MemTxResult;
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#endif
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