* target/arm: generate a custom MIDR for -cpu max * hw/misc/zynq_slcr: refactor to use standard register definition * Set ENET_BD_BDU in I.MX FEC controller * target/arm: Fix routing of singlestep exceptions * refactor a32/t32 decoder handling of PC * minor optimisations/cleanups of some a32/t32 codegen * target/arm/cpu64: Ensure kvm really supports aarch64=off * target/arm/cpu: Ensure we can use the pmu with kvm * target/arm: Minor cleanups preparatory to KVM SVE support -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl1WrIsZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tJ/D/9I0ccyciHwuekySUHs+Wq6 2grX8t6RFzlhA1ULoAaEO4x8uWWGnbiGTeSGM819T3nj1a7neQV12Xe5RRGG0j7n aeVseYnZF96oshKPkDSVTcGQisVfmmHIJ0oqx2k1aUGrmyFJlTuLWQBZCCiZKhxA zA6YzUbOA2apfi9nun6SbbjysiRD2lp2i9vI79nVlo+ca77v/1sdFUwzg0hRE//X IondHeWtCZScmc/GwABv4EdNzQ4Aerfe10v/pOKXEC59rPwEiaiSGBPu6SRUaGWH qHlwjVU2+BFGkz9Oy/7+tDTBk6saPi4taZF8SxxiC/QTyNV2ijyKV5iy9KOYAFw7 E41fhv4+Kch569/SX7fiyAxL0gAS2HGFtegByuQEgjjioOCRugFcX275NXvuW06j jfOP/zSD9P39WA0jCJaNj5FdJTcLmIuFxKjBUEX3Cdb+3igIq1BW0ZFd/OOBoo1W GHcEmO6tLyx35kigOb3TkayQpkqCoaGCcgzJ0g2Oy06rKwlcci+BfCfc3aG+uSSY +TuGjRhpQxQJJt880d7tBqeH9R5FABvQ0TEwGuACylDEZM5bN7BpZxCxCVN/bFG+ pzvzs/QtOq0FN7LK4L4rbuJui4nBhAyalbiIXQ8ihWQgmMqaYQSK8mXFgSZgizFl qATcYIr/q2gL4wHRos3XdA== =8BAF -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190816' into staging target-arm queue: * target/arm: generate a custom MIDR for -cpu max * hw/misc/zynq_slcr: refactor to use standard register definition * Set ENET_BD_BDU in I.MX FEC controller * target/arm: Fix routing of singlestep exceptions * refactor a32/t32 decoder handling of PC * minor optimisations/cleanups of some a32/t32 codegen * target/arm/cpu64: Ensure kvm really supports aarch64=off * target/arm/cpu: Ensure we can use the pmu with kvm * target/arm: Minor cleanups preparatory to KVM SVE support # gpg: Signature made Fri 16 Aug 2019 14:15:55 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190816: (29 commits) target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR target/arm: Use tcg_gen_rotri_i32 for gen_swap_half target/arm: Use ror32 instead of open-coding the operation target/arm: Remove redundant shift tests target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB target/arm: Use tcg_gen_extract_i32 for shifter_out_im target/arm/kvm64: Move the get/put of fpsimd registers out target/arm/kvm64: Fix error returns target/arm/cpu: Use div-round-up to determine predicate register array size target/arm/helper: zcr: Add build bug next to value range assumption target/arm/cpu: Ensure we can use the pmu with kvm target/arm/cpu64: Ensure kvm really supports aarch64=off target/arm: Remove helper_double_saturate target/arm: Use unallocated_encoding for aarch32 target/arm: Remove offset argument to gen_exception_bkpt_insn target/arm: Replace offset with pc in gen_exception_internal_insn target/arm: Replace offset with pc in gen_exception_insn target/arm: Replace s->pc with s->base.pc_next target/arm: Remove redundant s->pc & ~1 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
462 lines
13 KiB
C
462 lines
13 KiB
C
/*
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* Status and system control registers for Xilinx Zynq Platform
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Based on hw/arm_sysctl.c, written by Paul Brook
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "sysemu/runstate.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/registerfields.h"
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#ifndef ZYNQ_SLCR_ERR_DEBUG
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#define ZYNQ_SLCR_ERR_DEBUG 0
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#endif
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#define DB_PRINT(...) do { \
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if (ZYNQ_SLCR_ERR_DEBUG) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} \
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} while (0)
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#define XILINX_LOCK_KEY 0x767b
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#define XILINX_UNLOCK_KEY 0xdf0d
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REG32(SCL, 0x000)
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REG32(LOCK, 0x004)
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REG32(UNLOCK, 0x008)
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REG32(LOCKSTA, 0x00c)
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REG32(ARM_PLL_CTRL, 0x100)
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REG32(DDR_PLL_CTRL, 0x104)
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REG32(IO_PLL_CTRL, 0x108)
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REG32(PLL_STATUS, 0x10c)
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REG32(ARM_PLL_CFG, 0x110)
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REG32(DDR_PLL_CFG, 0x114)
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REG32(IO_PLL_CFG, 0x118)
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REG32(ARM_CLK_CTRL, 0x120)
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REG32(DDR_CLK_CTRL, 0x124)
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REG32(DCI_CLK_CTRL, 0x128)
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REG32(APER_CLK_CTRL, 0x12c)
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REG32(USB0_CLK_CTRL, 0x130)
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REG32(USB1_CLK_CTRL, 0x134)
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REG32(GEM0_RCLK_CTRL, 0x138)
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REG32(GEM1_RCLK_CTRL, 0x13c)
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REG32(GEM0_CLK_CTRL, 0x140)
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REG32(GEM1_CLK_CTRL, 0x144)
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REG32(SMC_CLK_CTRL, 0x148)
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REG32(LQSPI_CLK_CTRL, 0x14c)
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REG32(SDIO_CLK_CTRL, 0x150)
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REG32(UART_CLK_CTRL, 0x154)
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REG32(SPI_CLK_CTRL, 0x158)
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REG32(CAN_CLK_CTRL, 0x15c)
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REG32(CAN_MIOCLK_CTRL, 0x160)
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REG32(DBG_CLK_CTRL, 0x164)
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REG32(PCAP_CLK_CTRL, 0x168)
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REG32(TOPSW_CLK_CTRL, 0x16c)
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#define FPGA_CTRL_REGS(n, start) \
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REG32(FPGA ## n ## _CLK_CTRL, (start)) \
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REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
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REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\
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REG32(FPGA ## n ## _THR_STA, (start) + 0xc)
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FPGA_CTRL_REGS(0, 0x170)
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FPGA_CTRL_REGS(1, 0x180)
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FPGA_CTRL_REGS(2, 0x190)
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FPGA_CTRL_REGS(3, 0x1a0)
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REG32(BANDGAP_TRIP, 0x1b8)
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REG32(PLL_PREDIVISOR, 0x1c0)
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REG32(CLK_621_TRUE, 0x1c4)
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REG32(PSS_RST_CTRL, 0x200)
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FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
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REG32(DDR_RST_CTRL, 0x204)
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REG32(TOPSW_RESET_CTRL, 0x208)
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REG32(DMAC_RST_CTRL, 0x20c)
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REG32(USB_RST_CTRL, 0x210)
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REG32(GEM_RST_CTRL, 0x214)
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REG32(SDIO_RST_CTRL, 0x218)
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REG32(SPI_RST_CTRL, 0x21c)
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REG32(CAN_RST_CTRL, 0x220)
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REG32(I2C_RST_CTRL, 0x224)
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REG32(UART_RST_CTRL, 0x228)
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REG32(GPIO_RST_CTRL, 0x22c)
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REG32(LQSPI_RST_CTRL, 0x230)
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REG32(SMC_RST_CTRL, 0x234)
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REG32(OCM_RST_CTRL, 0x238)
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REG32(FPGA_RST_CTRL, 0x240)
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REG32(A9_CPU_RST_CTRL, 0x244)
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REG32(RS_AWDT_CTRL, 0x24c)
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REG32(RST_REASON, 0x250)
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REG32(REBOOT_STATUS, 0x258)
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REG32(BOOT_MODE, 0x25c)
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REG32(APU_CTRL, 0x300)
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REG32(WDT_CLK_SEL, 0x304)
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REG32(TZ_DMA_NS, 0x440)
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REG32(TZ_DMA_IRQ_NS, 0x444)
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REG32(TZ_DMA_PERIPH_NS, 0x448)
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REG32(PSS_IDCODE, 0x530)
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REG32(DDR_URGENT, 0x600)
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REG32(DDR_CAL_START, 0x60c)
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REG32(DDR_REF_START, 0x614)
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REG32(DDR_CMD_STA, 0x618)
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REG32(DDR_URGENT_SEL, 0x61c)
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REG32(DDR_DFI_STATUS, 0x620)
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REG32(MIO, 0x700)
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#define MIO_LENGTH 54
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REG32(MIO_LOOPBACK, 0x804)
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REG32(MIO_MST_TRI0, 0x808)
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REG32(MIO_MST_TRI1, 0x80c)
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REG32(SD0_WP_CD_SEL, 0x830)
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REG32(SD1_WP_CD_SEL, 0x834)
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REG32(LVL_SHFTR_EN, 0x900)
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REG32(OCM_CFG, 0x910)
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REG32(CPU_RAM, 0xa00)
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REG32(IOU, 0xa30)
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REG32(DMAC_RAM, 0xa50)
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REG32(AFI0, 0xa60)
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REG32(AFI1, 0xa6c)
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REG32(AFI2, 0xa78)
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REG32(AFI3, 0xa84)
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#define AFI_LENGTH 3
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REG32(OCM, 0xa90)
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REG32(DEVCI_RAM, 0xaa0)
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REG32(CSG_RAM, 0xab0)
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REG32(GPIOB_CTRL, 0xb00)
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REG32(GPIOB_CFG_CMOS18, 0xb04)
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REG32(GPIOB_CFG_CMOS25, 0xb08)
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REG32(GPIOB_CFG_CMOS33, 0xb0c)
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REG32(GPIOB_CFG_HSTL, 0xb14)
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REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
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REG32(DDRIOB, 0xb40)
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#define DDRIOB_LENGTH 14
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#define ZYNQ_SLCR_MMIO_SIZE 0x1000
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#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
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#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
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#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
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typedef struct ZynqSLCRState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[ZYNQ_SLCR_NUM_REGS];
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} ZynqSLCRState;
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static void zynq_slcr_reset(DeviceState *d)
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{
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ZynqSLCRState *s = ZYNQ_SLCR(d);
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int i;
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DB_PRINT("RESET\n");
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s->regs[R_LOCKSTA] = 1;
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/* 0x100 - 0x11C */
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s->regs[R_ARM_PLL_CTRL] = 0x0001A008;
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s->regs[R_DDR_PLL_CTRL] = 0x0001A008;
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s->regs[R_IO_PLL_CTRL] = 0x0001A008;
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s->regs[R_PLL_STATUS] = 0x0000003F;
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s->regs[R_ARM_PLL_CFG] = 0x00014000;
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s->regs[R_DDR_PLL_CFG] = 0x00014000;
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s->regs[R_IO_PLL_CFG] = 0x00014000;
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/* 0x120 - 0x16C */
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s->regs[R_ARM_CLK_CTRL] = 0x1F000400;
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s->regs[R_DDR_CLK_CTRL] = 0x18400003;
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s->regs[R_DCI_CLK_CTRL] = 0x01E03201;
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s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD;
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s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941;
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s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;
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s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01;
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s->regs[R_SMC_CLK_CTRL] = 0x00003C01;
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s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;
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s->regs[R_SDIO_CLK_CTRL] = 0x00001E03;
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s->regs[R_UART_CLK_CTRL] = 0x00003F03;
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s->regs[R_SPI_CLK_CTRL] = 0x00003F03;
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s->regs[R_CAN_CLK_CTRL] = 0x00501903;
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s->regs[R_DBG_CLK_CTRL] = 0x00000F03;
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s->regs[R_PCAP_CLK_CTRL] = 0x00000F01;
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/* 0x170 - 0x1AC */
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s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]
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= s->regs[R_FPGA2_CLK_CTRL]
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= s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;
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s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]
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= s->regs[R_FPGA2_THR_STA]
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= s->regs[R_FPGA3_THR_STA] = 0x00010000;
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/* 0x1B0 - 0x1D8 */
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s->regs[R_BANDGAP_TRIP] = 0x0000001F;
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s->regs[R_PLL_PREDIVISOR] = 0x00000001;
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s->regs[R_CLK_621_TRUE] = 0x00000001;
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/* 0x200 - 0x25C */
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s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F;
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s->regs[R_RST_REASON] = 0x00000040;
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s->regs[R_BOOT_MODE] = 0x00000001;
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/* 0x700 - 0x7D4 */
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for (i = 0; i < 54; i++) {
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s->regs[R_MIO + i] = 0x00001601;
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}
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for (i = 2; i <= 8; i++) {
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s->regs[R_MIO + i] = 0x00000601;
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}
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s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;
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s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]
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= s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]
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= 0x00010101;
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s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;
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s->regs[R_CPU_RAM + 6] = 0x00000001;
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s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]
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= s->regs[R_IOU + 3] = 0x09090909;
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s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;
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s->regs[R_IOU + 6] = 0x00000909;
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s->regs[R_DMAC_RAM] = 0x00000009;
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s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;
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s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;
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s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;
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s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;
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s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]
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= s->regs[R_AFI3 + 2] = 0x00000909;
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s->regs[R_OCM + 0] = 0x01010101;
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s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;
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s->regs[R_DEVCI_RAM] = 0x00000909;
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s->regs[R_CSG_RAM] = 0x00000001;
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s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]
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= s->regs[R_DDRIOB + 3] = 0x00000e00;
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s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]
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= 0x00000e00;
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s->regs[R_DDRIOB + 12] = 0x00000021;
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}
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static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
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{
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switch (offset) {
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case R_LOCK:
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case R_UNLOCK:
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case R_DDR_CAL_START:
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case R_DDR_REF_START:
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return !rnw; /* Write only */
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case R_LOCKSTA:
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case R_FPGA0_THR_STA:
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case R_FPGA1_THR_STA:
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case R_FPGA2_THR_STA:
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case R_FPGA3_THR_STA:
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case R_BOOT_MODE:
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case R_PSS_IDCODE:
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case R_DDR_CMD_STA:
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case R_DDR_DFI_STATUS:
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case R_PLL_STATUS:
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return rnw;/* read only */
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case R_SCL:
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case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:
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case R_ARM_PLL_CFG ... R_IO_PLL_CFG:
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case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:
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case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:
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case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:
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case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:
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case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:
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case R_BANDGAP_TRIP:
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case R_PLL_PREDIVISOR:
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case R_CLK_621_TRUE:
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case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:
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case R_RS_AWDT_CTRL:
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case R_RST_REASON:
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case R_REBOOT_STATUS:
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case R_APU_CTRL:
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case R_WDT_CLK_SEL:
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case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:
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case R_DDR_URGENT:
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case R_DDR_URGENT_SEL:
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case R_MIO ... R_MIO + MIO_LENGTH - 1:
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case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:
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case R_SD0_WP_CD_SEL:
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case R_SD1_WP_CD_SEL:
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case R_LVL_SHFTR_EN:
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case R_OCM_CFG:
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case R_CPU_RAM:
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case R_IOU:
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case R_DMAC_RAM:
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case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:
|
|
case R_OCM:
|
|
case R_DEVCI_RAM:
|
|
case R_CSG_RAM:
|
|
case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:
|
|
case R_GPIOB_CFG_HSTL:
|
|
case R_GPIOB_DRVR_BIAS_CTRL:
|
|
case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
|
|
unsigned size)
|
|
{
|
|
ZynqSLCRState *s = opaque;
|
|
offset /= 4;
|
|
uint32_t ret = s->regs[offset];
|
|
|
|
if (!zynq_slcr_check_offset(offset, true)) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
|
|
" addr %" HWADDR_PRIx "\n", offset * 4);
|
|
}
|
|
|
|
DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
|
|
return ret;
|
|
}
|
|
|
|
static void zynq_slcr_write(void *opaque, hwaddr offset,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
|
|
offset /= 4;
|
|
|
|
DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
|
|
|
|
if (!zynq_slcr_check_offset(offset, false)) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
|
|
"addr %" HWADDR_PRIx "\n", offset * 4);
|
|
return;
|
|
}
|
|
|
|
switch (offset) {
|
|
case R_SCL:
|
|
s->regs[R_SCL] = val & 0x1;
|
|
return;
|
|
case R_LOCK:
|
|
if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
|
|
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
|
|
(unsigned)val & 0xFFFF);
|
|
s->regs[R_LOCKSTA] = 1;
|
|
} else {
|
|
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
|
(int)offset, (unsigned)val & 0xFFFF);
|
|
}
|
|
return;
|
|
case R_UNLOCK:
|
|
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
|
|
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
|
|
(unsigned)val & 0xFFFF);
|
|
s->regs[R_LOCKSTA] = 0;
|
|
} else {
|
|
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
|
(int)offset, (unsigned)val & 0xFFFF);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (s->regs[R_LOCKSTA]) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"SCLR registers are locked. Unlock them first\n");
|
|
return;
|
|
}
|
|
s->regs[offset] = val;
|
|
|
|
switch (offset) {
|
|
case R_PSS_RST_CTRL:
|
|
if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps slcr_ops = {
|
|
.read = zynq_slcr_read,
|
|
.write = zynq_slcr_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void zynq_slcr_init(Object *obj)
|
|
{
|
|
ZynqSLCRState *s = ZYNQ_SLCR(obj);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
|
|
ZYNQ_SLCR_MMIO_SIZE);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_zynq_slcr = {
|
|
.name = "zynq_slcr",
|
|
.version_id = 2,
|
|
.minimum_version_id = 2,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void zynq_slcr_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_zynq_slcr;
|
|
dc->reset = zynq_slcr_reset;
|
|
}
|
|
|
|
static const TypeInfo zynq_slcr_info = {
|
|
.class_init = zynq_slcr_class_init,
|
|
.name = TYPE_ZYNQ_SLCR,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(ZynqSLCRState),
|
|
.instance_init = zynq_slcr_init,
|
|
};
|
|
|
|
static void zynq_slcr_register_types(void)
|
|
{
|
|
type_register_static(&zynq_slcr_info);
|
|
}
|
|
|
|
type_init(zynq_slcr_register_types)
|