This field was used for telling cpu_interrupt() to unlink a chain of TBs being executed when it worked that way. Now, cpu_interrupt() don't do this anymore. So we don't need this field anymore. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-Id: <1462273462-14036-1-git-send-email-sergey.fedorov@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
837 lines
26 KiB
C
837 lines
26 KiB
C
/*
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* QEMU CPU model
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_CPU_H
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#define QEMU_CPU_H
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#include "hw/qdev-core.h"
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#include "disas/bfd.h"
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#include "exec/hwaddr.h"
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#include "exec/memattrs.h"
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#include "qemu/queue.h"
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#include "qemu/thread.h"
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typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
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void *opaque);
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/**
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* vaddr:
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* Type wide enough to contain any #target_ulong virtual address.
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*/
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typedef uint64_t vaddr;
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#define VADDR_PRId PRId64
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#define VADDR_PRIu PRIu64
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#define VADDR_PRIo PRIo64
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#define VADDR_PRIx PRIx64
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#define VADDR_PRIX PRIX64
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#define VADDR_MAX UINT64_MAX
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/**
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* SECTION:cpu
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* @section_id: QEMU-cpu
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* @title: CPU Class
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* @short_description: Base class for all CPUs
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*/
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#define TYPE_CPU "cpu"
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/* Since this macro is used a lot in hot code paths and in conjunction with
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* FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
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* an unchecked cast.
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*/
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#define CPU(obj) ((CPUState *)(obj))
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#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
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#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
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typedef struct CPUWatchpoint CPUWatchpoint;
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typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec, int opaque,
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unsigned size);
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struct TranslationBlock;
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/**
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* CPUClass:
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* @class_by_name: Callback to map -cpu command line model name to an
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* instantiatable CPU type.
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* @parse_features: Callback to parse command line arguments.
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* @reset: Callback to reset the #CPUState to its initial state.
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* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
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* @has_work: Callback for checking if there is work to do.
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* @do_interrupt: Callback for interrupt handling.
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* @do_unassigned_access: Callback for unassigned access handling.
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* @do_unaligned_access: Callback for unaligned access handling, if
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* the target defines #ALIGNED_ONLY.
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* @virtio_is_big_endian: Callback to return %true if a CPU which supports
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* runtime configurable endianness is currently big-endian. Non-configurable
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* CPUs can use the default implementation of this method. This method should
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* not be used by any callers other than the pre-1.0 virtio devices.
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* @memory_rw_debug: Callback for GDB memory access.
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* @dump_state: Callback for dumping state.
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* @dump_statistics: Callback for dumping statistics.
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* @get_arch_id: Callback for getting architecture-dependent CPU ID.
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* @get_paging_enabled: Callback for inquiring whether paging is enabled.
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* @get_memory_mapping: Callback for obtaining the memory mappings.
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* @set_pc: Callback for setting the Program Counter register.
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* @synchronize_from_tb: Callback for synchronizing state from a TCG
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* #TranslationBlock.
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* @handle_mmu_fault: Callback for handling an MMU fault.
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* @get_phys_page_debug: Callback for obtaining a physical address.
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* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
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* associated memory transaction attributes to use for the access.
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* CPUs which use memory transaction attributes should implement this
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* instead of get_phys_page_debug.
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* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
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* a memory access with the specified memory transaction attributes.
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* @gdb_read_register: Callback for letting GDB read a register.
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* @gdb_write_register: Callback for letting GDB write a register.
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* @debug_check_watchpoint: Callback: return true if the architectural
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* watchpoint whose address has matched should really fire.
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* @debug_excp_handler: Callback for handling debug exceptions.
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* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
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* 64-bit VM coredump.
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* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
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* note to a 32-bit VM coredump.
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* @write_elf32_note: Callback for writing a CPU-specific ELF note to a
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* 32-bit VM coredump.
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* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
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* note to a 32-bit VM coredump.
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* @vmsd: State description for migration.
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* @gdb_num_core_regs: Number of core registers accessible to GDB.
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* @gdb_core_xml_file: File name for core registers GDB XML description.
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* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
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* before the insn which triggers a watchpoint rather than after it.
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* @gdb_arch_name: Optional callback that returns the architecture name known
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* to GDB. The caller must free the returned string with g_free.
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* @cpu_exec_enter: Callback for cpu_exec preparation.
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* @cpu_exec_exit: Callback for cpu_exec cleanup.
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* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
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* @disas_set_info: Setup architecture specific components of disassembly info
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*
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* Represents a CPU family or model.
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*/
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typedef struct CPUClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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ObjectClass *(*class_by_name)(const char *cpu_model);
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void (*parse_features)(CPUState *cpu, char *str, Error **errp);
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void (*reset)(CPUState *cpu);
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int reset_dump_flags;
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bool (*has_work)(CPUState *cpu);
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void (*do_interrupt)(CPUState *cpu);
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CPUUnassignedAccess do_unassigned_access;
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void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
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int is_write, int is_user, uintptr_t retaddr);
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bool (*virtio_is_big_endian)(CPUState *cpu);
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int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
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uint8_t *buf, int len, bool is_write);
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void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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void (*dump_statistics)(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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int64_t (*get_arch_id)(CPUState *cpu);
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bool (*get_paging_enabled)(const CPUState *cpu);
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void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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void (*set_pc)(CPUState *cpu, vaddr value);
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void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
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int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
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int mmu_index);
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hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
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hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
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int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
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int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
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bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
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void (*debug_excp_handler)(CPUState *cpu);
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int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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const struct VMStateDescription *vmsd;
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int gdb_num_core_regs;
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const char *gdb_core_xml_file;
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gchar * (*gdb_arch_name)(CPUState *cpu);
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bool gdb_stop_before_watchpoint;
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void (*cpu_exec_enter)(CPUState *cpu);
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void (*cpu_exec_exit)(CPUState *cpu);
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bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
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void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
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} CPUClass;
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#ifdef HOST_WORDS_BIGENDIAN
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typedef struct icount_decr_u16 {
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uint16_t high;
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uint16_t low;
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} icount_decr_u16;
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#else
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typedef struct icount_decr_u16 {
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uint16_t low;
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uint16_t high;
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} icount_decr_u16;
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#endif
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typedef struct CPUBreakpoint {
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vaddr pc;
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int flags; /* BP_* */
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QTAILQ_ENTRY(CPUBreakpoint) entry;
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} CPUBreakpoint;
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struct CPUWatchpoint {
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vaddr vaddr;
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vaddr len;
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vaddr hitaddr;
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MemTxAttrs hitattrs;
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int flags; /* BP_* */
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QTAILQ_ENTRY(CPUWatchpoint) entry;
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};
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struct KVMState;
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struct kvm_run;
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#define TB_JMP_CACHE_BITS 12
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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/**
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* CPUState:
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* @cpu_index: CPU index (informative).
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* @nr_cores: Number of cores within this CPU package.
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* @nr_threads: Number of threads within this CPU.
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* @numa_node: NUMA node this CPU is belonging to.
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* @host_tid: Host thread ID.
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* @running: #true if CPU is currently running (usermode).
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* @created: Indicates whether the CPU thread has been successfully created.
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* @interrupt_request: Indicates a pending interrupt request.
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* @halted: Nonzero if the CPU is in suspended state.
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* @stop: Indicates a pending stop request.
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* @stopped: Indicates the CPU has been artificially stopped.
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* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
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* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
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* CPU and return to its top level loop.
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* @tb_flushed: Indicates the translation buffer has been flushed.
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* @singlestep_enabled: Flags for single-stepping.
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* @icount_extra: Instructions until next timer event.
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* @icount_decr: Number of cycles left, with interrupt flag in high bit.
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* This allows a single read-compare-cbranch-write sequence to test
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* for both decrementer underflow and exceptions.
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* @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
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* requires that IO only be performed on the last instruction of a TB
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* so that interrupts take effect immediately.
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* @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
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* AddressSpaces this CPU has)
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* @num_ases: number of CPUAddressSpaces in @cpu_ases
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* @as: Pointer to the first AddressSpace, for the convenience of targets which
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* only have a single AddressSpace
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* @env_ptr: Pointer to subclass-specific CPUArchState field.
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* @gdb_regs: Additional GDB registers.
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* @gdb_num_regs: Number of total registers accessible to GDB.
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* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
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* @next_cpu: Next CPU sharing TB cache.
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* @opaque: User data.
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* @mem_io_pc: Host Program Counter at which the memory was accessed.
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* @mem_io_vaddr: Target virtual address at which the memory was accessed.
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* @kvm_fd: vCPU file descriptor for KVM.
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* @work_mutex: Lock to prevent multiple access to queued_work_*.
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* @queued_work_first: First asynchronous work pending.
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*
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* State of one CPU core or thread.
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*/
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struct CPUState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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int nr_cores;
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int nr_threads;
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int numa_node;
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struct QemuThread *thread;
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#ifdef _WIN32
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HANDLE hThread;
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#endif
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int thread_id;
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uint32_t host_tid;
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bool running;
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struct QemuCond *halt_cond;
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bool thread_kicked;
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bool created;
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bool stop;
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bool stopped;
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bool crash_occurred;
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bool exit_request;
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bool tb_flushed;
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uint32_t interrupt_request;
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int singlestep_enabled;
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int64_t icount_extra;
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sigjmp_buf jmp_env;
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QemuMutex work_mutex;
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struct qemu_work_item *queued_work_first, *queued_work_last;
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CPUAddressSpace *cpu_ases;
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int num_ases;
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AddressSpace *as;
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MemoryRegion *memory;
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void *env_ptr; /* CPUArchState */
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struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
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struct GDBRegisterState *gdb_regs;
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int gdb_num_regs;
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int gdb_num_g_regs;
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QTAILQ_ENTRY(CPUState) node;
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/* ice debug support */
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QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
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QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
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CPUWatchpoint *watchpoint_hit;
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void *opaque;
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/* In order to avoid passing too many arguments to the MMIO helpers,
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* we store some rarely used information in the CPU context.
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*/
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uintptr_t mem_io_pc;
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vaddr mem_io_vaddr;
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int kvm_fd;
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bool kvm_vcpu_dirty;
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struct KVMState *kvm_state;
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struct kvm_run *kvm_run;
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/* TODO Move common fields from CPUArchState here. */
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int cpu_index; /* used by alpha TCG */
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uint32_t halted; /* used by alpha, cris, ppc TCG */
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union {
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uint32_t u32;
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icount_decr_u16 u16;
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} icount_decr;
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uint32_t can_do_io;
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int32_t exception_index; /* used by m68k TCG */
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/* Used to keep track of an outstanding cpu throttle thread for migration
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* autoconverge
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*/
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bool throttle_thread_scheduled;
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/* Note that this is accessed at the start of every TB via a negative
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offset from AREG0. Leave this field at the end so as to make the
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(absolute value) offset as small as possible. This reduces code
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size, especially for hosts without large memory offsets. */
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uint32_t tcg_exit_req;
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};
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QTAILQ_HEAD(CPUTailQ, CPUState);
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extern struct CPUTailQ cpus;
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#define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
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#define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
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#define CPU_FOREACH_SAFE(cpu, next_cpu) \
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QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
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#define CPU_FOREACH_REVERSE(cpu) \
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QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
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#define first_cpu QTAILQ_FIRST(&cpus)
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extern __thread CPUState *current_cpu;
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/**
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* cpu_paging_enabled:
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* @cpu: The CPU whose state is to be inspected.
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*
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* Returns: %true if paging is enabled, %false otherwise.
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*/
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bool cpu_paging_enabled(const CPUState *cpu);
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/**
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* cpu_get_memory_mapping:
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* @cpu: The CPU whose memory mappings are to be obtained.
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* @list: Where to write the memory mappings to.
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* @errp: Pointer for reporting an #Error.
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*/
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void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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Error **errp);
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/**
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* cpu_write_elf64_note:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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/**
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* cpu_write_elf64_qemunote:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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/**
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* cpu_write_elf32_note:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque);
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/**
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* cpu_write_elf32_qemunote:
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* @f: pointer to a function that writes memory to a file
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* @cpu: The CPU whose memory is to be dumped
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* @cpuid: ID number of the CPU
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* @opaque: pointer to the CPUState struct
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*/
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int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque);
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/**
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* CPUDumpFlags:
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* @CPU_DUMP_CODE:
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* @CPU_DUMP_FPU: dump FPU register state, not just integer
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* @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
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*/
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enum CPUDumpFlags {
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CPU_DUMP_CODE = 0x00010000,
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CPU_DUMP_FPU = 0x00020000,
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CPU_DUMP_CCOP = 0x00040000,
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};
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/**
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* cpu_dump_state:
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* @cpu: The CPU whose state is to be dumped.
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* @f: File to dump to.
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* @cpu_fprintf: Function to dump with.
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* @flags: Flags what to dump.
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*
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* Dumps CPU state.
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*/
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void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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|
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/**
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|
* cpu_dump_statistics:
|
|
* @cpu: The CPU whose state is to be dumped.
|
|
* @f: File to dump to.
|
|
* @cpu_fprintf: Function to dump with.
|
|
* @flags: Flags what to dump.
|
|
*
|
|
* Dumps CPU statistics.
|
|
*/
|
|
void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
|
|
int flags);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
/**
|
|
* cpu_get_phys_page_attrs_debug:
|
|
* @cpu: The CPU to obtain the physical page address for.
|
|
* @addr: The virtual address.
|
|
* @attrs: Updated on return with the memory transaction attributes to use
|
|
* for this access.
|
|
*
|
|
* Obtains the physical page corresponding to a virtual one, together
|
|
* with the corresponding memory transaction attributes to use for the access.
|
|
* Use it only for debugging because no protection checks are done.
|
|
*
|
|
* Returns: Corresponding physical page address or -1 if no page found.
|
|
*/
|
|
static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
|
|
MemTxAttrs *attrs)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
if (cc->get_phys_page_attrs_debug) {
|
|
return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
|
|
}
|
|
/* Fallback for CPUs which don't implement the _attrs_ hook */
|
|
*attrs = MEMTXATTRS_UNSPECIFIED;
|
|
return cc->get_phys_page_debug(cpu, addr);
|
|
}
|
|
|
|
/**
|
|
* cpu_get_phys_page_debug:
|
|
* @cpu: The CPU to obtain the physical page address for.
|
|
* @addr: The virtual address.
|
|
*
|
|
* Obtains the physical page corresponding to a virtual one.
|
|
* Use it only for debugging because no protection checks are done.
|
|
*
|
|
* Returns: Corresponding physical page address or -1 if no page found.
|
|
*/
|
|
static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
|
|
{
|
|
MemTxAttrs attrs = {};
|
|
|
|
return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
|
|
}
|
|
|
|
/** cpu_asidx_from_attrs:
|
|
* @cpu: CPU
|
|
* @attrs: memory transaction attributes
|
|
*
|
|
* Returns the address space index specifying the CPU AddressSpace
|
|
* to use for a memory access with the given transaction attributes.
|
|
*/
|
|
static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
if (cc->asidx_from_attrs) {
|
|
return cc->asidx_from_attrs(cpu, attrs);
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* cpu_reset:
|
|
* @cpu: The CPU whose state is to be reset.
|
|
*/
|
|
void cpu_reset(CPUState *cpu);
|
|
|
|
/**
|
|
* cpu_class_by_name:
|
|
* @typename: The CPU base type.
|
|
* @cpu_model: The model string without any parameters.
|
|
*
|
|
* Looks up a CPU #ObjectClass matching name @cpu_model.
|
|
*
|
|
* Returns: A #CPUClass or %NULL if not matching class is found.
|
|
*/
|
|
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
|
|
|
|
/**
|
|
* cpu_generic_init:
|
|
* @typename: The CPU base type.
|
|
* @cpu_model: The model string including optional parameters.
|
|
*
|
|
* Instantiates a CPU, processes optional parameters and realizes the CPU.
|
|
*
|
|
* Returns: A #CPUState or %NULL if an error occurred.
|
|
*/
|
|
CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
|
|
|
|
/**
|
|
* cpu_has_work:
|
|
* @cpu: The vCPU to check.
|
|
*
|
|
* Checks whether the CPU has work to do.
|
|
*
|
|
* Returns: %true if the CPU has work, %false otherwise.
|
|
*/
|
|
static inline bool cpu_has_work(CPUState *cpu)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
g_assert(cc->has_work);
|
|
return cc->has_work(cpu);
|
|
}
|
|
|
|
/**
|
|
* qemu_cpu_is_self:
|
|
* @cpu: The vCPU to check against.
|
|
*
|
|
* Checks whether the caller is executing on the vCPU thread.
|
|
*
|
|
* Returns: %true if called from @cpu's thread, %false otherwise.
|
|
*/
|
|
bool qemu_cpu_is_self(CPUState *cpu);
|
|
|
|
/**
|
|
* qemu_cpu_kick:
|
|
* @cpu: The vCPU to kick.
|
|
*
|
|
* Kicks @cpu's thread.
|
|
*/
|
|
void qemu_cpu_kick(CPUState *cpu);
|
|
|
|
/**
|
|
* cpu_is_stopped:
|
|
* @cpu: The CPU to check.
|
|
*
|
|
* Checks whether the CPU is stopped.
|
|
*
|
|
* Returns: %true if run state is not running or if artificially stopped;
|
|
* %false otherwise.
|
|
*/
|
|
bool cpu_is_stopped(CPUState *cpu);
|
|
|
|
/**
|
|
* run_on_cpu:
|
|
* @cpu: The vCPU to run on.
|
|
* @func: The function to be executed.
|
|
* @data: Data to pass to the function.
|
|
*
|
|
* Schedules the function @func for execution on the vCPU @cpu.
|
|
*/
|
|
void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
|
|
|
|
/**
|
|
* async_run_on_cpu:
|
|
* @cpu: The vCPU to run on.
|
|
* @func: The function to be executed.
|
|
* @data: Data to pass to the function.
|
|
*
|
|
* Schedules the function @func for execution on the vCPU @cpu asynchronously.
|
|
*/
|
|
void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
|
|
|
|
/**
|
|
* qemu_get_cpu:
|
|
* @index: The CPUState@cpu_index value of the CPU to obtain.
|
|
*
|
|
* Gets a CPU matching @index.
|
|
*
|
|
* Returns: The CPU or %NULL if there is no matching CPU.
|
|
*/
|
|
CPUState *qemu_get_cpu(int index);
|
|
|
|
/**
|
|
* cpu_exists:
|
|
* @id: Guest-exposed CPU ID to lookup.
|
|
*
|
|
* Search for CPU with specified ID.
|
|
*
|
|
* Returns: %true - CPU is found, %false - CPU isn't found.
|
|
*/
|
|
bool cpu_exists(int64_t id);
|
|
|
|
/**
|
|
* cpu_throttle_set:
|
|
* @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
|
|
*
|
|
* Throttles all vcpus by forcing them to sleep for the given percentage of
|
|
* time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
|
|
* (example: 10ms sleep for every 30ms awake).
|
|
*
|
|
* cpu_throttle_set can be called as needed to adjust new_throttle_pct.
|
|
* Once the throttling starts, it will remain in effect until cpu_throttle_stop
|
|
* is called.
|
|
*/
|
|
void cpu_throttle_set(int new_throttle_pct);
|
|
|
|
/**
|
|
* cpu_throttle_stop:
|
|
*
|
|
* Stops the vcpu throttling started by cpu_throttle_set.
|
|
*/
|
|
void cpu_throttle_stop(void);
|
|
|
|
/**
|
|
* cpu_throttle_active:
|
|
*
|
|
* Returns: %true if the vcpus are currently being throttled, %false otherwise.
|
|
*/
|
|
bool cpu_throttle_active(void);
|
|
|
|
/**
|
|
* cpu_throttle_get_percentage:
|
|
*
|
|
* Returns the vcpu throttle percentage. See cpu_throttle_set for details.
|
|
*
|
|
* Returns: The throttle percentage in range 1 to 99.
|
|
*/
|
|
int cpu_throttle_get_percentage(void);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
typedef void (*CPUInterruptHandler)(CPUState *, int);
|
|
|
|
extern CPUInterruptHandler cpu_interrupt_handler;
|
|
|
|
/**
|
|
* cpu_interrupt:
|
|
* @cpu: The CPU to set an interrupt on.
|
|
* @mask: The interupts to set.
|
|
*
|
|
* Invokes the interrupt handler.
|
|
*/
|
|
static inline void cpu_interrupt(CPUState *cpu, int mask)
|
|
{
|
|
cpu_interrupt_handler(cpu, mask);
|
|
}
|
|
|
|
#else /* USER_ONLY */
|
|
|
|
void cpu_interrupt(CPUState *cpu, int mask);
|
|
|
|
#endif /* USER_ONLY */
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
|
|
bool is_write, bool is_exec,
|
|
int opaque, unsigned size)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
if (cc->do_unassigned_access) {
|
|
cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
|
|
}
|
|
}
|
|
|
|
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
|
|
int is_write, int is_user,
|
|
uintptr_t retaddr)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* cpu_set_pc:
|
|
* @cpu: The CPU to set the program counter for.
|
|
* @addr: Program counter value.
|
|
*
|
|
* Sets the program counter for a CPU.
|
|
*/
|
|
static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
|
|
{
|
|
CPUClass *cc = CPU_GET_CLASS(cpu);
|
|
|
|
cc->set_pc(cpu, addr);
|
|
}
|
|
|
|
/**
|
|
* cpu_reset_interrupt:
|
|
* @cpu: The CPU to clear the interrupt on.
|
|
* @mask: The interrupt mask to clear.
|
|
*
|
|
* Resets interrupts on the vCPU @cpu.
|
|
*/
|
|
void cpu_reset_interrupt(CPUState *cpu, int mask);
|
|
|
|
/**
|
|
* cpu_exit:
|
|
* @cpu: The CPU to exit.
|
|
*
|
|
* Requests the CPU @cpu to exit execution.
|
|
*/
|
|
void cpu_exit(CPUState *cpu);
|
|
|
|
/**
|
|
* cpu_resume:
|
|
* @cpu: The CPU to resume.
|
|
*
|
|
* Resumes CPU, i.e. puts CPU into runnable state.
|
|
*/
|
|
void cpu_resume(CPUState *cpu);
|
|
|
|
/**
|
|
* qemu_init_vcpu:
|
|
* @cpu: The vCPU to initialize.
|
|
*
|
|
* Initializes a vCPU.
|
|
*/
|
|
void qemu_init_vcpu(CPUState *cpu);
|
|
|
|
#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
|
|
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
|
|
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
|
|
|
|
/**
|
|
* cpu_single_step:
|
|
* @cpu: CPU to the flags for.
|
|
* @enabled: Flags to enable.
|
|
*
|
|
* Enables or disables single-stepping for @cpu.
|
|
*/
|
|
void cpu_single_step(CPUState *cpu, int enabled);
|
|
|
|
/* Breakpoint/watchpoint flags */
|
|
#define BP_MEM_READ 0x01
|
|
#define BP_MEM_WRITE 0x02
|
|
#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
|
|
#define BP_STOP_BEFORE_ACCESS 0x04
|
|
/* 0x08 currently unused */
|
|
#define BP_GDB 0x10
|
|
#define BP_CPU 0x20
|
|
#define BP_ANY (BP_GDB | BP_CPU)
|
|
#define BP_WATCHPOINT_HIT_READ 0x40
|
|
#define BP_WATCHPOINT_HIT_WRITE 0x80
|
|
#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
|
|
|
|
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
|
|
CPUBreakpoint **breakpoint);
|
|
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
|
|
void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
|
|
void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
|
|
|
|
/* Return true if PC matches an installed breakpoint. */
|
|
static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
|
|
{
|
|
CPUBreakpoint *bp;
|
|
|
|
if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
|
|
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
|
|
if (bp->pc == pc && (bp->flags & mask)) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
|
|
int flags, CPUWatchpoint **watchpoint);
|
|
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
|
|
vaddr len, int flags);
|
|
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
|
|
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
|
|
|
|
void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
|
|
GCC_FMT_ATTR(2, 3);
|
|
void cpu_exec_exit(CPUState *cpu);
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
extern const struct VMStateDescription vmstate_cpu_common;
|
|
#else
|
|
#define vmstate_cpu_common vmstate_dummy
|
|
#endif
|
|
|
|
#define VMSTATE_CPU() { \
|
|
.name = "parent_obj", \
|
|
.size = sizeof(CPUState), \
|
|
.vmsd = &vmstate_cpu_common, \
|
|
.flags = VMS_STRUCT, \
|
|
.offset = 0, \
|
|
}
|
|
|
|
#endif
|