qemu-patch-raspberry4/target/riscv
Michael Clark 33e3bc8d77
RISC-V: Hardwire satp to 0 for no-mmu case
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.

It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and more complex
trap handling code).

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06 10:39:38 +12:00
..
cpu.c RISC-V: Update E and I extension order 2018-05-06 10:39:38 +12:00
cpu.h RISC-V: Update E and I extension order 2018-05-06 10:39:38 +12:00
cpu_bits.h
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c RISC-V FPU Support 2018-03-07 08:30:28 +13:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.c RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Hardwire satp to 0 for no-mmu case 2018-05-06 10:39:38 +12:00
pmp.c RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V: Remove erroneous comment from translate.c 2018-05-06 10:39:38 +12:00