356a2db3c6
Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
296 lines
9.1 KiB
C
296 lines
9.1 KiB
C
/*
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* OpenRISC system instructions helper routines
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#define TO_SPR(group, number) (((group) << 11) + (number))
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void HELPER(mtspr)(CPUOpenRISCState *env,
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target_ulong ra, target_ulong rb, target_ulong offset)
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{
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#ifndef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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int spr = (ra | offset);
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int idx;
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switch (spr) {
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case TO_SPR(0, 0): /* VR */
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env->vr = rb;
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break;
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case TO_SPR(0, 11): /* EVBAR */
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env->evbar = rb;
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break;
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case TO_SPR(0, 16): /* NPC */
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cpu_restore_state(cs, GETPC());
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/* ??? Mirror or1ksim in not trashing delayed branch state
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when "jumping" to the current instruction. */
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if (env->pc != rb) {
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env->pc = rb;
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env->dflag = 0;
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cpu_loop_exit(cs);
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}
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break;
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case TO_SPR(0, 17): /* SR */
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if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
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(rb & (SR_IME | SR_DME | SR_SM))) {
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tlb_flush(cs);
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}
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cpu_set_sr(env, rb);
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if (env->sr & SR_DME) {
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env->tlb->cpu_openrisc_map_address_data =
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&cpu_openrisc_get_phys_data;
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} else {
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env->tlb->cpu_openrisc_map_address_data =
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&cpu_openrisc_get_phys_nommu;
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}
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if (env->sr & SR_IME) {
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env->tlb->cpu_openrisc_map_address_code =
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&cpu_openrisc_get_phys_code;
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} else {
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env->tlb->cpu_openrisc_map_address_code =
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&cpu_openrisc_get_phys_nommu;
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}
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break;
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case TO_SPR(0, 18): /* PPC */
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env->ppc = rb;
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break;
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case TO_SPR(0, 32): /* EPCR */
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env->epcr = rb;
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break;
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case TO_SPR(0, 48): /* EEAR */
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env->eear = rb;
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break;
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case TO_SPR(0, 64): /* ESR */
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env->esr = rb;
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break;
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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idx = spr - TO_SPR(1, 512);
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if (!(rb & 1)) {
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tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
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}
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env->tlb->dtlb[0][idx].mr = rb;
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break;
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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idx = spr - TO_SPR(1, 640);
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env->tlb->dtlb[0][idx].tr = rb;
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break;
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
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case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
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case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
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case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
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break;
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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idx = spr - TO_SPR(2, 512);
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if (!(rb & 1)) {
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tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
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}
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env->tlb->itlb[0][idx].mr = rb;
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break;
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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idx = spr - TO_SPR(2, 640);
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env->tlb->itlb[0][idx].tr = rb;
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break;
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
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case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
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case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
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case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
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break;
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case TO_SPR(5, 1): /* MACLO */
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env->mac = deposit64(env->mac, 0, 32, rb);
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break;
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case TO_SPR(5, 2): /* MACHI */
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env->mac = deposit64(env->mac, 32, 32, rb);
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break;
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case TO_SPR(9, 0): /* PICMR */
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env->picmr |= rb;
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break;
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case TO_SPR(9, 2): /* PICSR */
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env->picsr &= ~rb;
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break;
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case TO_SPR(10, 0): /* TTMR */
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{
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if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
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switch (rb & TTMR_M) {
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case TIMER_NONE:
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cpu_openrisc_count_stop(cpu);
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break;
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case TIMER_INTR:
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case TIMER_SHOT:
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case TIMER_CONT:
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cpu_openrisc_count_start(cpu);
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break;
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default:
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break;
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}
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}
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int ip = env->ttmr & TTMR_IP;
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if (rb & TTMR_IP) { /* Keep IP bit. */
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env->ttmr = (rb & ~TTMR_IP) | ip;
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} else { /* Clear IP bit. */
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env->ttmr = rb & ~TTMR_IP;
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cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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cpu_openrisc_timer_update(cpu);
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}
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break;
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case TO_SPR(10, 1): /* TTCR */
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env->ttcr = rb;
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if (env->ttmr & TIMER_NONE) {
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return;
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}
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cpu_openrisc_timer_update(cpu);
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break;
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default:
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break;
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}
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#endif
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}
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target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
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target_ulong rd, target_ulong ra, uint32_t offset)
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{
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#ifndef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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int spr = (ra | offset);
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int idx;
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switch (spr) {
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case TO_SPR(0, 0): /* VR */
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return env->vr & SPR_VR;
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case TO_SPR(0, 1): /* UPR */
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return env->upr; /* TT, DM, IM, UP present */
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case TO_SPR(0, 2): /* CPUCFGR */
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return env->cpucfgr;
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case TO_SPR(0, 3): /* DMMUCFGR */
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return env->dmmucfgr; /* 1Way, 64 entries */
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case TO_SPR(0, 4): /* IMMUCFGR */
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return env->immucfgr;
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case TO_SPR(0, 11): /* EVBAR */
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return env->evbar;
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case TO_SPR(0, 16): /* NPC (equals PC) */
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cpu_restore_state(cs, GETPC());
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return env->pc;
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case TO_SPR(0, 17): /* SR */
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return cpu_get_sr(env);
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case TO_SPR(0, 18): /* PPC */
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cpu_restore_state(cs, GETPC());
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return env->ppc;
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case TO_SPR(0, 32): /* EPCR */
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return env->epcr;
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case TO_SPR(0, 48): /* EEAR */
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return env->eear;
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case TO_SPR(0, 64): /* ESR */
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return env->esr;
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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idx = spr - TO_SPR(1, 512);
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return env->tlb->dtlb[0][idx].mr;
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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idx = spr - TO_SPR(1, 640);
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return env->tlb->dtlb[0][idx].tr;
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
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case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
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case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
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case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
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break;
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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idx = spr - TO_SPR(2, 512);
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return env->tlb->itlb[0][idx].mr;
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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idx = spr - TO_SPR(2, 640);
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return env->tlb->itlb[0][idx].tr;
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
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case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
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case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
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case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
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break;
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case TO_SPR(5, 1): /* MACLO */
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return (uint32_t)env->mac;
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break;
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case TO_SPR(5, 2): /* MACHI */
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return env->mac >> 32;
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break;
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case TO_SPR(9, 0): /* PICMR */
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return env->picmr;
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case TO_SPR(9, 2): /* PICSR */
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return env->picsr;
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case TO_SPR(10, 0): /* TTMR */
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return env->ttmr;
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case TO_SPR(10, 1): /* TTCR */
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cpu_openrisc_count_update(cpu);
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return env->ttcr;
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default:
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break;
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}
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#endif
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/* for rd is passed in, if rd unchanged, just keep it back. */
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return rd;
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}
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