Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with enough functionality to boot an aspeed_defconfig Linux kernel. The model implements the 'new' (revised) register set: While the hardware exposes both the new and legacy register sets, accesses to the model's legacy register set will not be serviced (however the access will be logged). [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49 lines
990 B
C
49 lines
990 B
C
/*
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* ASPEED Interrupt Controller (New)
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* Need to add SVIC and CVIC support
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*/
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#ifndef ASPEED_VIC_H
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#define ASPEED_VIC_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_VIC "aspeed.vic"
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#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
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#define ASPEED_VIC_NR_IRQS 51
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typedef struct AspeedVICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq fiq;
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uint64_t level;
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uint64_t raw;
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uint64_t select;
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uint64_t enable;
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uint64_t trigger;
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/* 0=edge, 1=level */
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uint64_t sense;
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/* 0=single-edge, 1=dual-edge */
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uint64_t dual_edge;
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/* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
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uint64_t event;
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} AspeedVICState;
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#endif /* ASPEED_VIC_H */
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