8d298bee09
disassembling relative branches in code which doesn't reside at what the guest CPU would think its execution address is. Use the new MapCodeAddress() API to tell libvixl where the code is from the guest CPU's point of view so it can get the target addresses right. Previous disassembly: 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x7f6cb7020434) 0x0000000040000004: aa1f03e1 mov x1, xzr 0x0000000040000008: aa1f03e2 mov x2, xzr 0x000000004000000c: aa1f03e3 mov x3, xzr 0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x7f6cb702042c) 0x0000000040000014: d61f0080 br x4 Fixed disassembly: 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018) 0x0000000040000004: aa1f03e1 mov x1, xzr 0x0000000040000008: aa1f03e2 mov x2, xzr 0x000000004000000c: aa1f03e3 mov x3, xzr 0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x40000020) 0x0000000040000014: d61f0080 br x4 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422274779-13359-3-git-send-email-peter.maydell@linaro.org
91 lines
2.5 KiB
C++
91 lines
2.5 KiB
C++
/*
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* ARM A64 disassembly output wrapper to libvixl
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* Copyright (c) 2013 Linaro Limited
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* Written by Claudio Fontana
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "a64/disasm-a64.h"
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extern "C" {
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#include "disas/bfd.h"
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}
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using namespace vixl;
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static Decoder *vixl_decoder = NULL;
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static Disassembler *vixl_disasm = NULL;
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/* We don't use libvixl's PrintDisassembler because its output
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* is a little unhelpful (trailing newlines, for example).
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* Instead we use our own very similar variant so we have
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* control over the format.
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*/
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class QEMUDisassembler : public Disassembler {
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public:
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explicit QEMUDisassembler(FILE *stream) : stream_(stream) { }
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~QEMUDisassembler() { }
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protected:
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virtual void ProcessOutput(const Instruction *instr) {
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fprintf(stream_, "%08" PRIx32 " %s",
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instr->InstructionBits(), GetOutput());
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}
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private:
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FILE *stream_;
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};
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static int vixl_is_initialized(void)
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{
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return vixl_decoder != NULL;
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}
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static void vixl_init(FILE *f) {
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vixl_decoder = new Decoder();
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vixl_disasm = new QEMUDisassembler(f);
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vixl_decoder->AppendVisitor(vixl_disasm);
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}
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#define INSN_SIZE 4
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/* Disassemble ARM A64 instruction. This is our only entry
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* point from QEMU's C code.
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*/
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int print_insn_arm_a64(uint64_t addr, disassemble_info *info)
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{
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uint8_t bytes[INSN_SIZE];
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uint32_t instrval;
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const Instruction *instr;
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int status;
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status = info->read_memory_func(addr, bytes, INSN_SIZE, info);
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if (status != 0) {
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info->memory_error_func(status, addr, info);
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return -1;
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}
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if (!vixl_is_initialized()) {
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vixl_init(info->stream);
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}
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instrval = bytes[0] | bytes[1] << 8 | bytes[2] << 16 | bytes[3] << 24;
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instr = reinterpret_cast<const Instruction *>(&instrval);
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vixl_disasm->MapCodeAddress(addr, instr);
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vixl_decoder->Decode(instr);
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return INSN_SIZE;
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}
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