haraldwolff/qemu-patch-raspberry4
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qemu-patch-raspberry4/target/riscv
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Thomas Huth 35c7f5254b target/riscv/vector_helper: Fix build on 32-bit big endian hosts 
The code currently fails to compile on 32-bit big endian hosts:

 target/riscv/vector_helper.c: In function 'vext_clear':
 target/riscv/vector_helper.c:154:16: error: cast to pointer from integer
 of different size [-Werror=int-to-pointer-cast]
         memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
                ^
 target/riscv/vector_helper.c:155:16: error: cast to pointer from integer
 of different size [-Werror=int-to-pointer-cast]
         memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
                ^
 cc1: all warnings being treated as errors

We should not use "long long" (i.e. 64-bit) values here to avoid the
problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead.

Fixes: 751538d5da ("add vector stride load and store instructions")
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200804170055.2851-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-05 10:43:45 +02:00
..
insn_trans target/riscv: fix vector index load/store constraints 2020-07-22 09:39:46 -07:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/riscv: configure and turn on vector extension from command line 2020-07-02 09:19:34 -07:00
cpu.h target/riscv: fix vill bit index in vtype register 2020-07-13 17:25:37 -07:00
cpu_bits.h target/riscv: support vector extension csr 2020-07-02 09:19:32 -07:00
cpu_helper.c target/riscv: Report errors validating 2nd-stage PTEs 2020-06-19 08:24:07 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: Fix the range of pmpcfg of CSR funcion table 2020-07-22 09:41:36 -07:00
fpu_helper.c target/riscv: vector floating-point classify instructions 2020-07-02 09:19:33 -07:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.h target/riscv: vector compress instruction 2020-07-02 09:19:34 -07:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode target/riscv: add vector amo operations 2020-07-02 09:19:33 -07:00
insn32.decode target/riscv: vector compress instruction 2020-07-02 09:19:34 -07:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: integer scalar move instruction 2020-07-02 09:19:33 -07:00
Makefile.objs target/riscv: add vector configure instruction 2020-07-02 09:19:32 -07:00
monitor.c target/riscv: Drop support for ISA spec version 1.09.1 2020-06-03 09:11:51 -07:00
op_helper.c target/riscv: Implement checks for hfence 2020-06-19 08:24:07 -07:00
pmp.c target/riscv: Fix pmp NA4 implementation 2020-07-13 17:25:37 -07:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-06-23 23:44:41 -07:00
trace-events target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-09-17 08:42:42 -07:00
translate.c target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
vector_helper.c target/riscv/vector_helper: Fix build on 32-bit big endian hosts 2020-08-05 10:43:45 +02:00