This bug showed up after 1455084ea2
, and
may be seen only on operating systems *not* using DMA to give commands
to SCSI adapter.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
773 lines
20 KiB
C
773 lines
20 KiB
C
/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "scsi.h"
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#include "esp.h"
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/* debug ESP card */
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, ...) \
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do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define ESP_ERROR(fmt, ...) \
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do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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#define ESP_REGS 16
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#define TI_BUFSZ 16
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typedef struct ESPState ESPState;
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struct ESPState {
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SysBusDevice busdev;
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uint32_t it_shift;
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qemu_irq irq;
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uint8_t rregs[ESP_REGS];
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uint8_t wregs[ESP_REGS];
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int32_t ti_size;
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uint32_t ti_rptr, ti_wptr;
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uint8_t ti_buf[TI_BUFSZ];
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uint32_t status;
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uint32_t dma;
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SCSIBus bus;
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SCSIDevice *current_dev;
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SCSIRequest *current_req;
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uint8_t cmdbuf[TI_BUFSZ];
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uint32_t cmdlen;
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uint32_t do_cmd;
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left;
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter;
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uint8_t *async_buf;
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uint32_t async_len;
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ESPDMAMemoryReadWriteFunc dma_memory_read;
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ESPDMAMemoryReadWriteFunc dma_memory_write;
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void *dma_opaque;
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int dma_enabled;
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void (*dma_cb)(ESPState *s);
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};
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#define ESP_TCLO 0x0
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#define ESP_TCMID 0x1
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#define ESP_FIFO 0x2
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#define ESP_CMD 0x3
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#define ESP_RSTAT 0x4
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#define ESP_WBUSID 0x4
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#define ESP_RINTR 0x5
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#define ESP_WSEL 0x5
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#define ESP_RSEQ 0x6
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#define ESP_WSYNTP 0x6
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#define ESP_RFLAGS 0x7
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#define ESP_WSYNO 0x7
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#define ESP_CFG1 0x8
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#define ESP_RRES1 0x9
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#define ESP_WCCF 0x9
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#define ESP_RRES2 0xa
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#define ESP_WTEST 0xa
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#define ESP_CFG2 0xb
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#define ESP_CFG3 0xc
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#define ESP_RES3 0xd
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#define ESP_TCHI 0xe
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#define ESP_RES4 0xf
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#define CMD_DMA 0x80
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#define CMD_CMD 0x7f
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#define CMD_NOP 0x00
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#define CMD_FLUSH 0x01
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#define CMD_RESET 0x02
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#define CMD_BUSRESET 0x03
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#define CMD_TI 0x10
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#define CMD_ICCS 0x11
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#define CMD_MSGACC 0x12
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#define CMD_PAD 0x18
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#define CMD_SATN 0x1a
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#define CMD_SEL 0x41
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#define CMD_SELATN 0x42
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#define CMD_SELATNS 0x43
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#define CMD_ENSEL 0x44
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MO 0x06
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#define STAT_MI 0x07
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#define STAT_PIO_MASK 0x06
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#define STAT_TC 0x10
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#define STAT_PE 0x20
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#define STAT_GE 0x40
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#define STAT_INT 0x80
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#define BUSID_DID 0x07
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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#define INTR_RST 0x80
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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#define CFG1_RESREPT 0x40
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#define TCHI_FAS100A 0x4
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static void esp_raise_irq(ESPState *s)
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{
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT;
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qemu_irq_raise(s->irq);
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DPRINTF("Raise IRQ\n");
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}
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}
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static void esp_lower_irq(ESPState *s)
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{
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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s->rregs[ESP_RSTAT] &= ~STAT_INT;
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qemu_irq_lower(s->irq);
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DPRINTF("Lower IRQ\n");
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}
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}
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static void esp_dma_enable(void *opaque, int irq, int level)
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{
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DeviceState *d = opaque;
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ESPState *s = container_of(d, ESPState, busdev.qdev);
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if (level) {
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s->dma_enabled = 1;
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DPRINTF("Raise enable\n");
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if (s->dma_cb) {
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s->dma_cb(s);
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s->dma_cb = NULL;
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}
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} else {
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DPRINTF("Lower enable\n");
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s->dma_enabled = 0;
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}
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}
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static void esp_request_cancelled(SCSIRequest *req)
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{
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ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
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if (req == s->current_req) {
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scsi_req_unref(s->current_req);
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s->current_req = NULL;
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s->current_dev = NULL;
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}
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}
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static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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{
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uint32_t dmalen;
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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if (s->dma) {
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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s->dma_memory_read(s->dma_opaque, buf, dmalen);
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} else {
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dmalen = s->ti_size;
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memcpy(buf, s->ti_buf, dmalen);
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buf[0] = buf[2] >> 5;
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}
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_dev) {
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/* Started a new command before the old one finished. Cancel it. */
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scsi_req_cancel(s->current_req);
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s->async_len = 0;
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}
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if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
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// No such drive
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
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esp_raise_irq(s);
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return 0;
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}
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s->current_dev = s->bus.devs[target];
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return dmalen;
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}
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static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
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{
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int32_t datalen;
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int lun;
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DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
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lun = busid & 7;
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s->current_req = scsi_req_new(s->current_dev, 0, lun);
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datalen = scsi_req_enqueue(s->current_req, buf);
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s->ti_size = datalen;
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if (datalen != 0) {
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s->rregs[ESP_RSTAT] = STAT_TC;
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) {
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s->rregs[ESP_RSTAT] |= STAT_DI;
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} else {
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s->rregs[ESP_RSTAT] |= STAT_DO;
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}
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scsi_req_continue(s->current_req);
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}
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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static void do_cmd(ESPState *s, uint8_t *buf)
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{
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uint8_t busid = buf[0];
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do_busid_cmd(s, &buf[1], busid);
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}
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static void handle_satn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn;
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return;
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}
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len = get_cmd(s, buf);
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if (len)
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do_cmd(s, buf);
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}
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static void handle_s_without_atn(ESPState *s)
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{
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_s_without_atn;
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return;
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}
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len = get_cmd(s, buf);
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if (len) {
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do_busid_cmd(s, buf, 0);
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}
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}
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static void handle_satn_stop(ESPState *s)
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{
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn_stop;
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return;
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}
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s->cmdlen = get_cmd(s, s->cmdbuf);
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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esp_raise_irq(s);
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}
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}
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static void write_response(ESPState *s)
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{
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DPRINTF("Transfer status (status=%d)\n", s->status);
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s->ti_buf[0] = s->status;
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s->ti_buf[1] = 0;
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if (s->dma) {
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s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[ESP_RFLAGS] = 2;
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}
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esp_raise_irq(s);
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}
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static void esp_dma_done(ESPState *s)
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{
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s->rregs[ESP_RSTAT] |= STAT_TC;
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s->rregs[ESP_RINTR] = INTR_BS;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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s->rregs[ESP_TCLO] = 0;
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s->rregs[ESP_TCMID] = 0;
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esp_raise_irq(s);
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}
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static void esp_do_dma(ESPState *s)
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{
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uint32_t len;
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int to_device;
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to_device = (s->ti_size < 0);
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len = s->dma_left;
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if (s->do_cmd) {
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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if (s->async_len == 0) {
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/* Defer until data is available. */
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return;
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}
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if (len > s->async_len) {
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len = s->async_len;
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}
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if (to_device) {
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s->dma_memory_read(s->dma_opaque, s->async_buf, len);
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} else {
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s->dma_memory_write(s->dma_opaque, s->async_buf, len);
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}
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s->dma_left -= len;
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s->async_buf += len;
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s->async_len -= len;
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if (to_device)
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s->ti_size += len;
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else
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s->ti_size -= len;
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if (s->async_len == 0) {
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scsi_req_continue(s->current_req);
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/* If there is still data to be read from the device then
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complete the DMA operation immediately. Otherwise defer
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until the scsi layer has completed. */
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if (to_device || s->dma_left != 0 || s->ti_size == 0) {
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return;
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}
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}
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s);
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}
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static void esp_command_complete(SCSIRequest *req, uint32_t status)
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{
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ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0) {
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DPRINTF("SCSI command completed unexpectedly\n");
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}
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (status) {
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DPRINTF("Command failed\n");
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}
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s->status = status;
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s->rregs[ESP_RSTAT] = STAT_ST;
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esp_dma_done(s);
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if (s->current_req) {
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scsi_req_unref(s->current_req);
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s->current_req = NULL;
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s->current_dev = NULL;
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}
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}
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static void esp_transfer_data(SCSIRequest *req, uint32_t len)
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{
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ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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s->async_len = len;
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s->async_buf = scsi_req_get_buf(req);
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if (s->dma_left) {
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esp_do_dma(s);
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} else if (s->dma_counter != 0 && s->ti_size <= 0) {
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/* If this was the last part of a DMA transfer then the
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completion interrupt is deferred to here. */
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esp_dma_done(s);
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}
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}
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static void handle_ti(ESPState *s)
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{
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uint32_t dmalen, minlen;
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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if (dmalen==0) {
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dmalen=0x10000;
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}
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s->dma_counter = dmalen;
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if (s->do_cmd)
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minlen = (dmalen < 32) ? dmalen : 32;
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else if (s->ti_size < 0)
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minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
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else
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minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
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DPRINTF("Transfer Information len %d\n", minlen);
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if (s->dma) {
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s->dma_left = minlen;
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s->rregs[ESP_RSTAT] &= ~STAT_TC;
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esp_do_dma(s);
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} else if (s->do_cmd) {
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DPRINTF("command len %d\n", s->cmdlen);
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf);
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return;
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}
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}
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static void esp_hard_reset(DeviceState *d)
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{
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ESPState *s = container_of(d, ESPState, busdev.qdev);
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memset(s->rregs, 0, ESP_REGS);
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memset(s->wregs, 0, ESP_REGS);
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s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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s->dma_cb = NULL;
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s->rregs[ESP_CFG1] = 7;
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}
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static void esp_soft_reset(DeviceState *d)
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{
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ESPState *s = container_of(d, ESPState, busdev.qdev);
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qemu_irq_lower(s->irq);
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esp_hard_reset(d);
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}
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static void parent_esp_reset(void *opaque, int irq, int level)
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{
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if (level) {
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esp_soft_reset(opaque);
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|
}
|
|
}
|
|
|
|
static void esp_gpio_demux(void *opaque, int irq, int level)
|
|
{
|
|
switch (irq) {
|
|
case 0:
|
|
parent_esp_reset(opaque, irq, level);
|
|
break;
|
|
case 1:
|
|
esp_dma_enable(opaque, irq, level);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
ESPState *s = opaque;
|
|
uint32_t saddr, old_val;
|
|
|
|
saddr = addr >> s->it_shift;
|
|
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
|
switch (saddr) {
|
|
case ESP_FIFO:
|
|
if (s->ti_size > 0) {
|
|
s->ti_size--;
|
|
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
|
|
/* Data out. */
|
|
ESP_ERROR("PIO data read not implemented\n");
|
|
s->rregs[ESP_FIFO] = 0;
|
|
} else {
|
|
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
|
|
}
|
|
esp_raise_irq(s);
|
|
}
|
|
if (s->ti_size == 0) {
|
|
s->ti_rptr = 0;
|
|
s->ti_wptr = 0;
|
|
}
|
|
break;
|
|
case ESP_RINTR:
|
|
/* Clear sequence step, interrupt register and all status bits
|
|
except TC */
|
|
old_val = s->rregs[ESP_RINTR];
|
|
s->rregs[ESP_RINTR] = 0;
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
|
esp_lower_irq(s);
|
|
|
|
return old_val;
|
|
default:
|
|
break;
|
|
}
|
|
return s->rregs[saddr];
|
|
}
|
|
|
|
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
ESPState *s = opaque;
|
|
uint32_t saddr;
|
|
|
|
saddr = addr >> s->it_shift;
|
|
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
|
val);
|
|
switch (saddr) {
|
|
case ESP_TCLO:
|
|
case ESP_TCMID:
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
break;
|
|
case ESP_FIFO:
|
|
if (s->do_cmd) {
|
|
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
|
} else if (s->ti_size == TI_BUFSZ - 1) {
|
|
ESP_ERROR("fifo overrun\n");
|
|
} else {
|
|
s->ti_size++;
|
|
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
|
}
|
|
break;
|
|
case ESP_CMD:
|
|
s->rregs[saddr] = val;
|
|
if (val & CMD_DMA) {
|
|
s->dma = 1;
|
|
/* Reload DMA counter. */
|
|
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
|
|
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
|
|
} else {
|
|
s->dma = 0;
|
|
}
|
|
switch(val & CMD_CMD) {
|
|
case CMD_NOP:
|
|
DPRINTF("NOP (%2.2x)\n", val);
|
|
break;
|
|
case CMD_FLUSH:
|
|
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
|
//s->ti_size = 0;
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
break;
|
|
case CMD_RESET:
|
|
DPRINTF("Chip reset (%2.2x)\n", val);
|
|
esp_soft_reset(&s->busdev.qdev);
|
|
break;
|
|
case CMD_BUSRESET:
|
|
DPRINTF("Bus reset (%2.2x)\n", val);
|
|
s->rregs[ESP_RINTR] = INTR_RST;
|
|
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
|
esp_raise_irq(s);
|
|
}
|
|
break;
|
|
case CMD_TI:
|
|
handle_ti(s);
|
|
break;
|
|
case CMD_ICCS:
|
|
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
|
write_response(s);
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSTAT] |= STAT_MI;
|
|
break;
|
|
case CMD_MSGACC:
|
|
DPRINTF("Message Accepted (%2.2x)\n", val);
|
|
s->rregs[ESP_RINTR] = INTR_DC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
esp_raise_irq(s);
|
|
break;
|
|
case CMD_PAD:
|
|
DPRINTF("Transfer padding (%2.2x)\n", val);
|
|
s->rregs[ESP_RSTAT] = STAT_TC;
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
break;
|
|
case CMD_SATN:
|
|
DPRINTF("Set ATN (%2.2x)\n", val);
|
|
break;
|
|
case CMD_SEL:
|
|
DPRINTF("Select without ATN (%2.2x)\n", val);
|
|
handle_s_without_atn(s);
|
|
break;
|
|
case CMD_SELATN:
|
|
DPRINTF("Select with ATN (%2.2x)\n", val);
|
|
handle_satn(s);
|
|
break;
|
|
case CMD_SELATNS:
|
|
DPRINTF("Select with ATN & stop (%2.2x)\n", val);
|
|
handle_satn_stop(s);
|
|
break;
|
|
case CMD_ENSEL:
|
|
DPRINTF("Enable selection (%2.2x)\n", val);
|
|
s->rregs[ESP_RINTR] = 0;
|
|
break;
|
|
default:
|
|
ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
|
break;
|
|
}
|
|
break;
|
|
case ESP_WBUSID ... ESP_WSYNO:
|
|
break;
|
|
case ESP_CFG1:
|
|
s->rregs[saddr] = val;
|
|
break;
|
|
case ESP_WCCF ... ESP_WTEST:
|
|
break;
|
|
case ESP_CFG2 ... ESP_RES4:
|
|
s->rregs[saddr] = val;
|
|
break;
|
|
default:
|
|
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
|
return;
|
|
}
|
|
s->wregs[saddr] = val;
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const esp_mem_read[3] = {
|
|
esp_mem_readb,
|
|
NULL,
|
|
NULL,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const esp_mem_write[3] = {
|
|
esp_mem_writeb,
|
|
NULL,
|
|
esp_mem_writeb,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_esp = {
|
|
.name ="esp",
|
|
.version_id = 3,
|
|
.minimum_version_id = 3,
|
|
.minimum_version_id_old = 3,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_BUFFER(rregs, ESPState),
|
|
VMSTATE_BUFFER(wregs, ESPState),
|
|
VMSTATE_INT32(ti_size, ESPState),
|
|
VMSTATE_UINT32(ti_rptr, ESPState),
|
|
VMSTATE_UINT32(ti_wptr, ESPState),
|
|
VMSTATE_BUFFER(ti_buf, ESPState),
|
|
VMSTATE_UINT32(status, ESPState),
|
|
VMSTATE_UINT32(dma, ESPState),
|
|
VMSTATE_BUFFER(cmdbuf, ESPState),
|
|
VMSTATE_UINT32(cmdlen, ESPState),
|
|
VMSTATE_UINT32(do_cmd, ESPState),
|
|
VMSTATE_UINT32(dma_left, ESPState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
void esp_init(target_phys_addr_t espaddr, int it_shift,
|
|
ESPDMAMemoryReadWriteFunc dma_memory_read,
|
|
ESPDMAMemoryReadWriteFunc dma_memory_write,
|
|
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
|
|
qemu_irq *dma_enable)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
ESPState *esp;
|
|
|
|
dev = qdev_create(NULL, "esp");
|
|
esp = DO_UPCAST(ESPState, busdev.qdev, dev);
|
|
esp->dma_memory_read = dma_memory_read;
|
|
esp->dma_memory_write = dma_memory_write;
|
|
esp->dma_opaque = dma_opaque;
|
|
esp->it_shift = it_shift;
|
|
/* XXX for now until rc4030 has been changed to use DMA enable signal */
|
|
esp->dma_enabled = 1;
|
|
qdev_init_nofail(dev);
|
|
s = sysbus_from_qdev(dev);
|
|
sysbus_connect_irq(s, 0, irq);
|
|
sysbus_mmio_map(s, 0, espaddr);
|
|
*reset = qdev_get_gpio_in(dev, 0);
|
|
*dma_enable = qdev_get_gpio_in(dev, 1);
|
|
}
|
|
|
|
static const struct SCSIBusOps esp_scsi_ops = {
|
|
.transfer_data = esp_transfer_data,
|
|
.complete = esp_command_complete,
|
|
.cancel = esp_request_cancelled
|
|
};
|
|
|
|
static int esp_init1(SysBusDevice *dev)
|
|
{
|
|
ESPState *s = FROM_SYSBUS(ESPState, dev);
|
|
int esp_io_memory;
|
|
|
|
sysbus_init_irq(dev, &s->irq);
|
|
assert(s->it_shift != -1);
|
|
|
|
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
|
|
|
|
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
|
|
|
|
scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops);
|
|
return scsi_bus_legacy_handle_cmdline(&s->bus);
|
|
}
|
|
|
|
static SysBusDeviceInfo esp_info = {
|
|
.init = esp_init1,
|
|
.qdev.name = "esp",
|
|
.qdev.size = sizeof(ESPState),
|
|
.qdev.vmsd = &vmstate_esp,
|
|
.qdev.reset = esp_hard_reset,
|
|
.qdev.props = (Property[]) {
|
|
{.name = NULL}
|
|
}
|
|
};
|
|
|
|
static void esp_register_devices(void)
|
|
{
|
|
sysbus_register_withprop(&esp_info);
|
|
}
|
|
|
|
device_init(esp_register_devices)
|