changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
176 lines
4.9 KiB
C
176 lines
4.9 KiB
C
/*
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* QEMU TILE-Gx CPU
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*
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* Copyright (c) 2015 Chen Gang
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#include "linux-user/syscall_defs.h"
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#include "exec/exec-all.h"
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static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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static const char * const reg_names[TILEGX_R_COUNT] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
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};
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TileGXCPU *cpu = TILEGX_CPU(cs);
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CPUTLGState *env = &cpu->env;
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int i;
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for (i = 0; i < TILEGX_R_COUNT; i++) {
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cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
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reg_names[i], env->regs[i],
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(i % 4) == 3 ? "\n" : " ");
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}
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cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
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env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
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}
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static ObjectClass *tilegx_cpu_class_by_name(const char *cpu_model)
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{
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return object_class_by_name(TYPE_TILEGX_CPU);
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}
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static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
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{
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TileGXCPU *cpu = TILEGX_CPU(cs);
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cpu->env.pc = value;
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}
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static bool tilegx_cpu_has_work(CPUState *cs)
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{
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return true;
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}
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static void tilegx_cpu_reset(CPUState *s)
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{
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TileGXCPU *cpu = TILEGX_CPU(s);
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TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
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CPUTLGState *env = &cpu->env;
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tcc->parent_reset(s);
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memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
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}
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static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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tcc->parent_realize(dev, errp);
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}
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static void tilegx_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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TileGXCPU *cpu = TILEGX_CPU(obj);
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CPUTLGState *env = &cpu->env;
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cs->env_ptr = env;
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}
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static void tilegx_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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{
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TileGXCPU *cpu = TILEGX_CPU(cs);
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/* The sigcode field will be filled in by do_signal in main.c. */
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cs->exception_index = TILEGX_EXCP_SIGNAL;
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cpu->env.excaddr = address;
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cpu->env.signo = TARGET_SIGSEGV;
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cpu->env.sigcode = 0;
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return 1;
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}
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static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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tilegx_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
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&tcc->parent_realize);
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tcc->parent_reset = cc->reset;
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cc->reset = tilegx_cpu_reset;
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cc->class_by_name = tilegx_cpu_class_by_name;
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cc->has_work = tilegx_cpu_has_work;
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cc->do_interrupt = tilegx_cpu_do_interrupt;
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cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
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cc->dump_state = tilegx_cpu_dump_state;
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cc->set_pc = tilegx_cpu_set_pc;
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cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
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cc->gdb_num_core_regs = 0;
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cc->tcg_initialize = tilegx_tcg_init;
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}
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static const TypeInfo tilegx_cpu_type_info = {
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.name = TYPE_TILEGX_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(TileGXCPU),
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.instance_init = tilegx_cpu_initfn,
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.class_size = sizeof(TileGXCPUClass),
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.class_init = tilegx_cpu_class_init,
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};
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static void tilegx_cpu_register_types(void)
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{
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type_register_static(&tilegx_cpu_type_info);
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}
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type_init(tilegx_cpu_register_types)
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