qemu-patch-raspberry4/hw/riscv
Alistair Francis 6911fde410 riscv/virt: Increase flash size
Coreboot developers have requested that they have at least 32MB of flash
to load binaries. We currently have 32MB of flash, but it is split in
two to allow loading two flash binaries. Let's increase the flash size
from 32MB to 64MB to ensure we have a single region that is 32MB.

No QEMU release has include flash in the RISC-V virt machine, so this
isn't a breaking change.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-11-14 09:53:28 -08:00
..
boot.c riscv/boot: Fix possible memory leak 2019-10-28 08:46:06 -07:00
Kconfig riscv/virt: Add the PFlash CFI01 device 2019-10-28 07:47:28 -07:00
Makefile.objs riscv: sifive: Implement a model for SiFive FU540 OTP 2019-09-17 08:42:49 -07:00
riscv_hart.c riscv: hart: Add a "hartid-base" property to RISC-V hart array 2019-09-17 08:42:47 -07:00
riscv_htif.c hw: Do not include "exec/address-spaces.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sifive_clint.c Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
sifive_e.c riscv: sifive_e: Drop sifive_mmio_emulate() 2019-09-17 08:42:46 -07:00
sifive_e_prci.c riscv: sifive_e: prci: Update the PRCI register block size 2019-09-17 08:42:46 -07:00
sifive_gpio.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
sifive_plic.c riscv: plic: Remove unused interrupt functions 2019-09-17 08:42:42 -07:00
sifive_test.c riscv: hw: Remove the unnecessary include of target/riscv/cpu.h 2019-09-17 08:42:45 -07:00
sifive_u.c riscv/sifive_u: Add the start-in-flash property 2019-10-28 07:47:28 -07:00
sifive_u_otp.c riscv: sifive: Implement a model for SiFive FU540 OTP 2019-09-17 08:42:49 -07:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_uart.c riscv: hw: Remove the unnecessary include of target/riscv/cpu.h 2019-09-17 08:42:45 -07:00
spike.c riscv: hw: Drop "clock-frequency" property of cpu nodes 2019-10-28 07:47:27 -07:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
virt.c riscv/virt: Increase flash size 2019-11-14 09:53:28 -08:00