Refactor the monitor API and prepare it for decoupled terminals: term_print functions are renamed to monitor_* and all monitor services gain a new parameter (mon) that will once refer to the monitor instance the output is supposed to appear on. However, the argument remains unused for now. All monitor command callbacks are also extended by a mon parameter so that command handlers are able to pass an appropriate reference to monitor output services. For the case that monitor outputs so far happen without clearly identifiable context, the global variable cur_mon is introduced that shall once provide a pointer either to the current active monitor (while processing commands) or to the default one. On the mid or long term, those use case will be obsoleted so that this variable can be removed again. Due to the broad usage of the monitor interface, this patch mostly deals with converting users of the monitor API. A few of them are already extended to pass 'mon' from the command handler further down to internal functions that invoke monitor_printf. At this chance, monitor-related prototypes are moved from console.h to a new monitor.h. The same is done for the readline API. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6711 c046a42c-6fe2-441c-8c8c-71466251a162
420 lines
12 KiB
C
420 lines
12 KiB
C
/*
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* QEMU Sparc SLAVIO interrupt controller emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "monitor.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("IRQ: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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/*
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* Registers of interrupt controller in sun4m.
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*
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* This is the interrupt controller part of chip STP2001 (Slave I/O), also
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* produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* There is a system master controller and one for each cpu.
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*
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*/
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#define MAX_CPUS 16
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#define MAX_PILS 16
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struct SLAVIO_CPUINTCTLState;
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typedef struct SLAVIO_INTCTLState {
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uint32_t intregm_pending;
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uint32_t intregm_disabled;
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uint32_t target_cpu;
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count[32];
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#endif
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qemu_irq *cpu_irqs[MAX_CPUS];
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const uint32_t *intbit_to_level;
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uint32_t cputimer_lbit, cputimer_mbit;
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uint32_t pil_out[MAX_CPUS];
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struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
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} SLAVIO_INTCTLState;
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typedef struct SLAVIO_CPUINTCTLState {
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uint32_t intreg_pending;
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SLAVIO_INTCTLState *master;
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uint32_t cpu;
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} SLAVIO_CPUINTCTLState;
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#define INTCTL_MAXADDR 0xf
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#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
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#define INTCTLM_SIZE 0x14
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#define MASTER_IRQ_MASK ~0x0fa2007f
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#define MASTER_DISABLE 0x80000000
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#define CPU_SOFTIRQ_MASK 0xfffe0000
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#define CPU_HARDIRQ_MASK 0x0000fffe
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#define CPU_IRQ_INT15_IN 0x0004000
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#define CPU_IRQ_INT15_MASK 0x80000000
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
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// per-cpu interrupt controller
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static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_CPUINTCTLState *s = opaque;
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uint32_t saddr, ret;
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saddr = addr >> 2;
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switch (saddr) {
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case 0:
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ret = s->intreg_pending;
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break;
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default:
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ret = 0;
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break;
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}
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DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
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return ret;
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}
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SLAVIO_CPUINTCTLState *s = opaque;
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uint32_t saddr;
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saddr = addr >> 2;
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DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
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switch (saddr) {
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case 1: // clear pending softints
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if (val & CPU_IRQ_INT15_IN)
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val |= CPU_IRQ_INT15_MASK;
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val &= CPU_SOFTIRQ_MASK;
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s->intreg_pending &= ~val;
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slavio_check_interrupts(s->master);
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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s->intreg_pending);
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break;
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case 2: // set softint
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val &= CPU_SOFTIRQ_MASK;
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s->intreg_pending |= val;
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slavio_check_interrupts(s->master);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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s->intreg_pending);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
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NULL,
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NULL,
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slavio_intctl_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
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NULL,
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NULL,
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slavio_intctl_mem_writel,
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};
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// master system interrupt controller
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static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr, ret;
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saddr = addr >> 2;
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switch (saddr) {
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case 0:
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ret = s->intregm_pending & ~MASTER_DISABLE;
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break;
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case 1:
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ret = s->intregm_disabled & MASTER_IRQ_MASK;
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break;
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case 4:
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ret = s->target_cpu;
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break;
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default:
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ret = 0;
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break;
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}
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DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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saddr = addr >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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switch (saddr) {
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case 2: // clear (enable)
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// Force clear unused bits
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val &= MASTER_IRQ_MASK;
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s->intregm_disabled &= ~val;
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled);
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slavio_check_interrupts(s);
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break;
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case 3: // set (disable, clear pending)
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// Force clear unused bits
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val &= MASTER_IRQ_MASK;
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s->intregm_disabled |= val;
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s->intregm_pending &= ~val;
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slavio_check_interrupts(s);
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DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled);
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break;
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case 4:
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s->target_cpu = val & (MAX_CPUS - 1);
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slavio_check_interrupts(s);
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DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
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NULL,
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NULL,
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slavio_intctlm_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
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NULL,
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NULL,
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slavio_intctlm_mem_writel,
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};
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void slavio_pic_info(Monitor *mon, void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
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s->slaves[i]->intreg_pending);
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}
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monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
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s->intregm_pending, s->intregm_disabled);
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}
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void slavio_irq_info(Monitor *mon, void *opaque)
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{
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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SLAVIO_INTCTLState *s = opaque;
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int i;
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int64_t count;
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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count = s->irq_count[i];
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if (count > 0)
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monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
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}
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#endif
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}
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
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{
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uint32_t pending = s->intregm_pending, pil_pending;
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unsigned int i, j;
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pending &= ~s->intregm_disabled;
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DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
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for (i = 0; i < MAX_CPUS; i++) {
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pil_pending = 0;
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if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
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(i == s->target_cpu)) {
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for (j = 0; j < 32; j++) {
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if (pending & (1 << j))
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pil_pending |= 1 << s->intbit_to_level[j];
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}
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}
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pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
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for (j = 0; j < MAX_PILS; j++) {
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if (pil_pending & (1 << j)) {
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if (!(s->pil_out[i] & (1 << j)))
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qemu_irq_raise(s->cpu_irqs[i][j]);
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} else {
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if (s->pil_out[i] & (1 << j))
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qemu_irq_lower(s->cpu_irqs[i][j]);
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}
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}
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s->pil_out[i] = pil_pending;
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}
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}
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/*
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* "irq" here is the bit number in the system interrupt register to
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* separate serial and keyboard interrupts sharing a level.
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*/
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static void slavio_set_irq(void *opaque, int irq, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = s->intbit_to_level[irq];
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DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
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level);
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if (pil > 0) {
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if (level) {
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[pil]++;
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#endif
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s->intregm_pending |= mask;
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s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
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} else {
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s->intregm_pending &= ~mask;
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s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
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}
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slavio_check_interrupts(s);
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}
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}
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static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
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if (level) {
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s->intregm_pending |= s->cputimer_mbit;
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s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
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} else {
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s->intregm_pending &= ~s->cputimer_mbit;
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s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
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}
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slavio_check_interrupts(s);
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}
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static void slavio_intctl_save(QEMUFile *f, void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
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}
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qemu_put_be32s(f, &s->intregm_pending);
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qemu_put_be32s(f, &s->intregm_disabled);
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qemu_put_be32s(f, &s->target_cpu);
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}
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static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
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}
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qemu_get_be32s(f, &s->intregm_pending);
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qemu_get_be32s(f, &s->intregm_disabled);
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qemu_get_be32s(f, &s->target_cpu);
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slavio_check_interrupts(s);
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return 0;
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}
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static void slavio_intctl_reset(void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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s->slaves[i]->intreg_pending = 0;
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}
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s->intregm_disabled = ~MASTER_IRQ_MASK;
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s->intregm_pending = 0;
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s->target_cpu = 0;
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slavio_check_interrupts(s);
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}
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void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
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const uint32_t *intbit_to_level,
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qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq, unsigned int cputimer)
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{
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int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
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SLAVIO_INTCTLState *s;
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SLAVIO_CPUINTCTLState *slave;
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s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
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s->intbit_to_level = intbit_to_level;
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for (i = 0; i < MAX_CPUS; i++) {
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slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
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slave->cpu = i;
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slave->master = s;
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slavio_intctl_io_memory = cpu_register_io_memory(0,
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slavio_intctl_mem_read,
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slavio_intctl_mem_write,
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slave);
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cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
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slavio_intctl_io_memory);
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s->slaves[i] = slave;
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s->cpu_irqs[i] = parent_irq[i];
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}
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slavio_intctlm_io_memory = cpu_register_io_memory(0,
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slavio_intctlm_mem_read,
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slavio_intctlm_mem_write,
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s);
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cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
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register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
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slavio_intctl_load, s);
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qemu_register_reset(slavio_intctl_reset, s);
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*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
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*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
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s->cputimer_mbit = 1 << cputimer;
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s->cputimer_lbit = 1 << intbit_to_level[cputimer];
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slavio_intctl_reset(s);
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return s;
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}
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