The NetCanReceive handler return whether the device can or can not receive new packets. Make it obvious by returning a boolean type. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
756 lines
21 KiB
C
756 lines
21 KiB
C
/*
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* QEMU Intel i82596 (Apricot) emulation
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*
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* Copyright (c) 2019 Helge Deller <deller@gmx.de>
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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* This software was written to be compatible with the specification:
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* https://www.intel.com/assets/pdf/general/82596ca.pdf
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "net/net.h"
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#include "net/eth.h"
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#include "sysemu/sysemu.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "i82596.h"
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#include <zlib.h> /* For crc32 */
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#if defined(ENABLE_DEBUG)
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#define DBG(x) x
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#else
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#define DBG(x) do { } while (0)
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#endif
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#define USE_TIMER 0
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
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#define PKT_BUF_SZ 1536
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#define MAX_MC_CNT 64
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#define ISCP_BUSY 0x0001
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#define I596_NULL ((uint32_t)0xffffffff)
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#define SCB_STATUS_CX 0x8000 /* CU finished command with I bit */
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#define SCB_STATUS_FR 0x4000 /* RU finished receiving a frame */
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#define SCB_STATUS_CNA 0x2000 /* CU left active state */
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#define SCB_STATUS_RNR 0x1000 /* RU left active state */
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#define SCB_COMMAND_ACK_MASK \
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(SCB_STATUS_CX | SCB_STATUS_FR | SCB_STATUS_CNA | SCB_STATUS_RNR)
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#define CU_IDLE 0
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#define CU_SUSPENDED 1
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#define CU_ACTIVE 2
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#define RX_IDLE 0
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#define RX_SUSPENDED 1
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#define RX_READY 4
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#define CMD_EOL 0x8000 /* The last command of the list, stop. */
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#define CMD_SUSP 0x4000 /* Suspend after doing cmd. */
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#define CMD_INTR 0x2000 /* Interrupt after doing cmd. */
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#define CMD_FLEX 0x0008 /* Enable flexible memory model */
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enum commands {
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CmdNOp = 0, CmdSASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,
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CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7
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};
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#define STAT_C 0x8000 /* Set to 0 after execution */
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#define STAT_B 0x4000 /* Command being executed */
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#define STAT_OK 0x2000 /* Command executed ok */
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#define STAT_A 0x1000 /* Command aborted */
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#define I596_EOF 0x8000
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#define SIZE_MASK 0x3fff
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#define ETHER_TYPE_LEN 2
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#define VLAN_TCI_LEN 2
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#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
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/* various flags in the chip config registers */
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#define I596_PREFETCH (s->config[0] & 0x80)
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#define I596_PROMISC (s->config[8] & 0x01)
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#define I596_BC_DISABLE (s->config[8] & 0x02) /* broadcast disable */
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#define I596_NOCRC_INS (s->config[8] & 0x08)
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#define I596_CRCINM (s->config[11] & 0x04) /* CRC appended */
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#define I596_MC_ALL (s->config[11] & 0x20)
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#define I596_MULTIIA (s->config[13] & 0x40)
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static uint8_t get_byte(uint32_t addr)
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{
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return ldub_phys(&address_space_memory, addr);
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}
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static void set_byte(uint32_t addr, uint8_t c)
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{
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return stb_phys(&address_space_memory, addr, c);
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}
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static uint16_t get_uint16(uint32_t addr)
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{
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return lduw_be_phys(&address_space_memory, addr);
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}
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static void set_uint16(uint32_t addr, uint16_t w)
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{
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return stw_be_phys(&address_space_memory, addr, w);
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}
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static uint32_t get_uint32(uint32_t addr)
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{
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uint32_t lo = lduw_be_phys(&address_space_memory, addr);
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uint32_t hi = lduw_be_phys(&address_space_memory, addr + 2);
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return (hi << 16) | lo;
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}
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static void set_uint32(uint32_t addr, uint32_t val)
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{
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set_uint16(addr, (uint16_t) val);
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set_uint16(addr + 2, val >> 16);
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}
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struct qemu_ether_header {
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uint8_t ether_dhost[6];
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uint8_t ether_shost[6];
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uint16_t ether_type;
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};
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#define PRINT_PKTHDR(txt, BUF) do { \
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struct qemu_ether_header *hdr = (void *)(BUF); \
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printf(txt ": packet dhost=" MAC_FMT ", shost=" MAC_FMT ", type=0x%04x\n",\
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MAC_ARG(hdr->ether_dhost), MAC_ARG(hdr->ether_shost), \
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be16_to_cpu(hdr->ether_type)); \
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} while (0)
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static void i82596_transmit(I82596State *s, uint32_t addr)
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{
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uint32_t tdb_p; /* Transmit Buffer Descriptor */
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/* TODO: Check flexible mode */
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tdb_p = get_uint32(addr + 8);
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while (tdb_p != I596_NULL) {
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uint16_t size, len;
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uint32_t tba;
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size = get_uint16(tdb_p);
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len = size & SIZE_MASK;
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tba = get_uint32(tdb_p + 8);
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trace_i82596_transmit(len, tba);
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if (s->nic && len) {
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assert(len <= sizeof(s->tx_buffer));
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address_space_read(&address_space_memory, tba,
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MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len);
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DBG(PRINT_PKTHDR("Send", &s->tx_buffer));
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DBG(printf("Sending %d bytes\n", len));
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qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len);
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}
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/* was this the last package? */
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if (size & I596_EOF) {
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break;
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}
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/* get next buffer pointer */
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tdb_p = get_uint32(tdb_p + 4);
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}
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}
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static void set_individual_address(I82596State *s, uint32_t addr)
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{
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NetClientState *nc;
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uint8_t *m;
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nc = qemu_get_queue(s->nic);
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m = s->conf.macaddr.a;
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address_space_read(&address_space_memory, addr + 8,
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MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN);
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qemu_format_nic_info_str(nc, m);
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trace_i82596_new_mac(nc->info_str);
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}
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static void set_multicast_list(I82596State *s, uint32_t addr)
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{
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uint16_t mc_count, i;
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memset(&s->mult[0], 0, sizeof(s->mult));
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mc_count = get_uint16(addr + 8) / ETH_ALEN;
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addr += 10;
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if (mc_count > MAX_MC_CNT) {
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mc_count = MAX_MC_CNT;
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}
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for (i = 0; i < mc_count; i++) {
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uint8_t multicast_addr[ETH_ALEN];
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address_space_read(&address_space_memory, addr + i * ETH_ALEN,
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MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN);
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DBG(printf("Add multicast entry " MAC_FMT "\n",
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MAC_ARG(multicast_addr)));
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unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) &
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BITS(7, 2)) >> 2;
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assert(mcast_idx < 8 * sizeof(s->mult));
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s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
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}
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trace_i82596_set_multicast(mc_count);
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}
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void i82596_set_link_status(NetClientState *nc)
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{
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I82596State *d = qemu_get_nic_opaque(nc);
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d->lnkst = nc->link_down ? 0 : 0x8000;
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}
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static void update_scb_status(I82596State *s)
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{
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s->scb_status = (s->scb_status & 0xf000)
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| (s->cu_status << 8) | (s->rx_status << 4);
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set_uint16(s->scb, s->scb_status);
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}
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static void i82596_s_reset(I82596State *s)
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{
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trace_i82596_s_reset(s);
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s->scp = 0;
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s->scb_status = 0;
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s->cu_status = CU_IDLE;
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s->rx_status = RX_SUSPENDED;
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s->cmd_p = I596_NULL;
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s->lnkst = 0x8000; /* initial link state: up */
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s->ca = s->ca_active = 0;
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s->send_irq = 0;
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}
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static void command_loop(I82596State *s)
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{
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uint16_t cmd;
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uint16_t status;
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uint8_t byte_cnt;
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DBG(printf("STARTING COMMAND LOOP cmd_p=%08x\n", s->cmd_p));
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while (s->cmd_p != I596_NULL) {
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/* set status */
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status = STAT_B;
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set_uint16(s->cmd_p, status);
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status = STAT_C | STAT_OK; /* update, but write later */
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cmd = get_uint16(s->cmd_p + 2);
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DBG(printf("Running command %04x at %08x\n", cmd, s->cmd_p));
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switch (cmd & 0x07) {
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case CmdNOp:
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break;
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case CmdSASetup:
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set_individual_address(s, s->cmd_p);
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break;
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case CmdConfigure:
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byte_cnt = get_byte(s->cmd_p + 8) & 0x0f;
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byte_cnt = MAX(byte_cnt, 4);
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byte_cnt = MIN(byte_cnt, sizeof(s->config));
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/* copy byte_cnt max. */
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address_space_read(&address_space_memory, s->cmd_p + 8,
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MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt);
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/* config byte according to page 35ff */
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s->config[2] &= 0x82; /* mask valid bits */
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s->config[2] |= 0x40;
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s->config[7] &= 0xf7; /* clear zero bit */
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assert(I596_NOCRC_INS == 0); /* do CRC insertion */
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s->config[10] = MAX(s->config[10], 5); /* min frame length */
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s->config[12] &= 0x40; /* only full duplex field valid */
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s->config[13] |= 0x3f; /* set ones in byte 13 */
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break;
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case CmdTDR:
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/* get signal LINK */
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set_uint32(s->cmd_p + 8, s->lnkst);
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break;
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case CmdTx:
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i82596_transmit(s, s->cmd_p);
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break;
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case CmdMulticastList:
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set_multicast_list(s, s->cmd_p);
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break;
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case CmdDump:
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case CmdDiagnose:
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printf("FIXME Command %d !!\n", cmd & 7);
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assert(0);
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}
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/* update status */
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set_uint16(s->cmd_p, status);
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s->cmd_p = get_uint32(s->cmd_p + 4); /* get link address */
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DBG(printf("NEXT addr would be %08x\n", s->cmd_p));
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if (s->cmd_p == 0) {
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s->cmd_p = I596_NULL;
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}
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/* Stop when last command of the list. */
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if (cmd & CMD_EOL) {
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s->cmd_p = I596_NULL;
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}
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/* Suspend after doing cmd? */
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if (cmd & CMD_SUSP) {
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s->cu_status = CU_SUSPENDED;
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printf("FIXME SUSPEND !!\n");
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}
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/* Interrupt after doing cmd? */
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if (cmd & CMD_INTR) {
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s->scb_status |= SCB_STATUS_CX;
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} else {
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s->scb_status &= ~SCB_STATUS_CX;
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}
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update_scb_status(s);
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/* Interrupt after doing cmd? */
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if (cmd & CMD_INTR) {
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s->send_irq = 1;
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}
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if (s->cu_status != CU_ACTIVE) {
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break;
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}
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}
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DBG(printf("FINISHED COMMAND LOOP\n"));
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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static void i82596_flush_queue_timer(void *opaque)
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{
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I82596State *s = opaque;
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if (0) {
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timer_del(s->flush_queue_timer);
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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timer_mod(s->flush_queue_timer,
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qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000);
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}
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}
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static void examine_scb(I82596State *s)
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{
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uint16_t command, cuc, ruc;
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/* get the scb command word */
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command = get_uint16(s->scb + 2);
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cuc = (command >> 8) & 0x7;
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ruc = (command >> 4) & 0x7;
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DBG(printf("MAIN COMMAND %04x cuc %02x ruc %02x\n", command, cuc, ruc));
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/* and clear the scb command word */
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set_uint16(s->scb + 2, 0);
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s->scb_status &= ~(command & SCB_COMMAND_ACK_MASK);
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switch (cuc) {
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case 0: /* no change */
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break;
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case 1: /* CUC_START */
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s->cu_status = CU_ACTIVE;
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break;
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case 4: /* CUC_ABORT */
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s->cu_status = CU_SUSPENDED;
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s->scb_status |= SCB_STATUS_CNA; /* CU left active state */
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break;
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default:
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printf("WARNING: Unknown CUC %d!\n", cuc);
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}
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switch (ruc) {
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case 0: /* no change */
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break;
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case 1: /* RX_START */
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case 2: /* RX_RESUME */
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s->rx_status = RX_IDLE;
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if (USE_TIMER) {
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timer_mod(s->flush_queue_timer, qemu_clock_get_ms(
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QEMU_CLOCK_VIRTUAL) + 1000);
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}
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break;
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case 3: /* RX_SUSPEND */
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case 4: /* RX_ABORT */
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s->rx_status = RX_SUSPENDED;
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s->scb_status |= SCB_STATUS_RNR; /* RU left active state */
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break;
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default:
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printf("WARNING: Unknown RUC %d!\n", ruc);
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}
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if (command & 0x80) { /* reset bit set? */
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i82596_s_reset(s);
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}
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/* execute commands from SCBL */
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if (s->cu_status != CU_SUSPENDED) {
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if (s->cmd_p == I596_NULL) {
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s->cmd_p = get_uint32(s->scb + 4);
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}
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}
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/* update scb status */
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update_scb_status(s);
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command_loop(s);
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}
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static void signal_ca(I82596State *s)
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{
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uint32_t iscp = 0;
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/* trace_i82596_channel_attention(s); */
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if (s->scp) {
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/* CA after reset -> do init with new scp. */
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s->sysbus = get_byte(s->scp + 3); /* big endian */
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DBG(printf("SYSBUS = %08x\n", s->sysbus));
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if (((s->sysbus >> 1) & 0x03) != 2) {
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printf("WARNING: NO LINEAR MODE !!\n");
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}
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if ((s->sysbus >> 7)) {
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printf("WARNING: 32BIT LINMODE IN B-STEPPING NOT SUPPORTED !!\n");
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}
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iscp = get_uint32(s->scp + 8);
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s->scb = get_uint32(iscp + 4);
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set_byte(iscp + 1, 0); /* clear BUSY flag in iscp */
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s->scp = 0;
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}
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s->ca++; /* count ca() */
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if (!s->ca_active) {
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s->ca_active = 1;
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while (s->ca) {
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examine_scb(s);
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s->ca--;
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}
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s->ca_active = 0;
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}
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if (s->send_irq) {
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s->send_irq = 0;
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qemu_set_irq(s->irq, 1);
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}
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}
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void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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I82596State *s = opaque;
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/* printf("i82596_ioport_writew addr=0x%08x val=0x%04x\n", addr, val); */
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switch (addr) {
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case PORT_RESET: /* Reset */
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i82596_s_reset(s);
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break;
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case PORT_ALTSCP:
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s->scp = val;
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break;
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case PORT_CA:
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signal_ca(s);
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break;
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}
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}
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uint32_t i82596_ioport_readw(void *opaque, uint32_t addr)
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{
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return -1;
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}
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void i82596_h_reset(void *opaque)
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{
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I82596State *s = opaque;
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i82596_s_reset(s);
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}
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bool i82596_can_receive(NetClientState *nc)
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{
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I82596State *s = qemu_get_nic_opaque(nc);
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if (s->rx_status == RX_SUSPENDED) {
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return false;
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}
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if (!s->lnkst) {
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return false;
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}
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if (USE_TIMER && !timer_pending(s->flush_queue_timer)) {
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return true;
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}
|
|
|
|
return true;
|
|
}
|
|
|
|
#define MIN_BUF_SIZE 60
|
|
|
|
ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz)
|
|
{
|
|
I82596State *s = qemu_get_nic_opaque(nc);
|
|
uint32_t rfd_p;
|
|
uint32_t rbd;
|
|
uint16_t is_broadcast = 0;
|
|
size_t len = sz; /* length of data for guest (including CRC) */
|
|
size_t bufsz = sz; /* length of data in buf */
|
|
uint32_t crc;
|
|
uint8_t *crc_ptr;
|
|
uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
|
|
static const uint8_t broadcast_macaddr[6] = {
|
|
0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
|
|
|
DBG(printf("i82596_receive() start\n"));
|
|
|
|
if (USE_TIMER && timer_pending(s->flush_queue_timer)) {
|
|
return 0;
|
|
}
|
|
|
|
/* first check if receiver is enabled */
|
|
if (s->rx_status == RX_SUSPENDED) {
|
|
trace_i82596_receive_analysis(">>> Receiving suspended");
|
|
return -1;
|
|
}
|
|
|
|
if (!s->lnkst) {
|
|
trace_i82596_receive_analysis(">>> Link down");
|
|
return -1;
|
|
}
|
|
|
|
/* Received frame smaller than configured "min frame len"? */
|
|
if (sz < s->config[10]) {
|
|
printf("Received frame too small, %zu vs. %u bytes\n",
|
|
sz, s->config[10]);
|
|
return -1;
|
|
}
|
|
|
|
DBG(printf("Received %lu bytes\n", sz));
|
|
|
|
if (I596_PROMISC) {
|
|
|
|
/* promiscuous: receive all */
|
|
trace_i82596_receive_analysis(
|
|
">>> packet received in promiscuous mode");
|
|
|
|
} else {
|
|
|
|
if (!memcmp(buf, broadcast_macaddr, 6)) {
|
|
/* broadcast address */
|
|
if (I596_BC_DISABLE) {
|
|
trace_i82596_receive_analysis(">>> broadcast packet rejected");
|
|
|
|
return len;
|
|
}
|
|
|
|
trace_i82596_receive_analysis(">>> broadcast packet received");
|
|
is_broadcast = 1;
|
|
|
|
} else if (buf[0] & 0x01) {
|
|
/* multicast */
|
|
if (!I596_MC_ALL) {
|
|
trace_i82596_receive_analysis(">>> multicast packet rejected");
|
|
|
|
return len;
|
|
}
|
|
|
|
int mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2;
|
|
assert(mcast_idx < 8 * sizeof(s->mult));
|
|
|
|
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
|
|
trace_i82596_receive_analysis(">>> multicast address mismatch");
|
|
|
|
return len;
|
|
}
|
|
|
|
trace_i82596_receive_analysis(">>> multicast packet received");
|
|
is_broadcast = 1;
|
|
|
|
} else if (!memcmp(s->conf.macaddr.a, buf, 6)) {
|
|
|
|
/* match */
|
|
trace_i82596_receive_analysis(
|
|
">>> physical address matching packet received");
|
|
|
|
} else {
|
|
|
|
trace_i82596_receive_analysis(">>> unknown packet");
|
|
|
|
return len;
|
|
}
|
|
}
|
|
|
|
/* if too small buffer, then expand it */
|
|
if (len < MIN_BUF_SIZE + VLAN_HLEN) {
|
|
memcpy(buf1, buf, len);
|
|
memset(buf1 + len, 0, MIN_BUF_SIZE + VLAN_HLEN - len);
|
|
buf = buf1;
|
|
if (len < MIN_BUF_SIZE) {
|
|
len = MIN_BUF_SIZE;
|
|
}
|
|
bufsz = len;
|
|
}
|
|
|
|
/* Calculate the ethernet checksum (4 bytes) */
|
|
len += 4;
|
|
crc = cpu_to_be32(crc32(~0, buf, sz));
|
|
crc_ptr = (uint8_t *) &crc;
|
|
|
|
rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */
|
|
assert(rfd_p && rfd_p != I596_NULL);
|
|
|
|
/* get first Receive Buffer Descriptor Address */
|
|
rbd = get_uint32(rfd_p + 8);
|
|
assert(rbd && rbd != I596_NULL);
|
|
|
|
trace_i82596_receive_packet(len);
|
|
/* PRINT_PKTHDR("Receive", buf); */
|
|
|
|
while (len) {
|
|
uint16_t command, status;
|
|
uint32_t next_rfd;
|
|
|
|
command = get_uint16(rfd_p + 2);
|
|
assert(command & CMD_FLEX); /* assert Flex Mode */
|
|
/* get first Receive Buffer Descriptor Address */
|
|
rbd = get_uint32(rfd_p + 8);
|
|
assert(get_uint16(rfd_p + 14) == 0);
|
|
|
|
/* printf("Receive: rfd is %08x\n", rfd_p); */
|
|
|
|
while (len) {
|
|
uint16_t buffer_size, num;
|
|
uint32_t rba;
|
|
size_t bufcount, crccount;
|
|
|
|
/* printf("Receive: rbd is %08x\n", rbd); */
|
|
buffer_size = get_uint16(rbd + 12);
|
|
/* printf("buffer_size is 0x%x\n", buffer_size); */
|
|
assert(buffer_size != 0);
|
|
|
|
num = buffer_size & SIZE_MASK;
|
|
if (num > len) {
|
|
num = len;
|
|
}
|
|
rba = get_uint32(rbd + 8);
|
|
/* printf("rba is 0x%x\n", rba); */
|
|
/*
|
|
* Calculate how many bytes we want from buf[] and how many
|
|
* from the CRC.
|
|
*/
|
|
if ((len - num) >= 4) {
|
|
/* The whole guest buffer, we haven't hit the CRC yet */
|
|
bufcount = num;
|
|
} else {
|
|
/* All that's left of buf[] */
|
|
bufcount = len - 4;
|
|
}
|
|
crccount = num - bufcount;
|
|
|
|
if (bufcount > 0) {
|
|
/* Still some of the actual data buffer to transfer */
|
|
assert(bufsz >= bufcount);
|
|
bufsz -= bufcount;
|
|
address_space_write(&address_space_memory, rba,
|
|
MEMTXATTRS_UNSPECIFIED, buf, bufcount);
|
|
rba += bufcount;
|
|
buf += bufcount;
|
|
len -= bufcount;
|
|
}
|
|
|
|
/* Write as much of the CRC as fits */
|
|
if (crccount > 0) {
|
|
address_space_write(&address_space_memory, rba,
|
|
MEMTXATTRS_UNSPECIFIED, crc_ptr, crccount);
|
|
rba += crccount;
|
|
crc_ptr += crccount;
|
|
len -= crccount;
|
|
}
|
|
|
|
num |= 0x4000; /* set F BIT */
|
|
if (len == 0) {
|
|
num |= I596_EOF; /* set EOF BIT */
|
|
}
|
|
set_uint16(rbd + 0, num); /* write actual count with flags */
|
|
|
|
/* get next rbd */
|
|
rbd = get_uint32(rbd + 4);
|
|
/* printf("Next Receive: rbd is %08x\n", rbd); */
|
|
|
|
if (buffer_size & I596_EOF) /* last entry */
|
|
break;
|
|
}
|
|
|
|
/* Housekeeping, see pg. 18 */
|
|
next_rfd = get_uint32(rfd_p + 4);
|
|
set_uint32(next_rfd + 8, rbd);
|
|
|
|
status = STAT_C | STAT_OK | is_broadcast;
|
|
set_uint16(rfd_p, status);
|
|
|
|
if (command & CMD_SUSP) { /* suspend after command? */
|
|
s->rx_status = RX_SUSPENDED;
|
|
s->scb_status |= SCB_STATUS_RNR; /* RU left active state */
|
|
break;
|
|
}
|
|
if (command & CMD_EOL) /* was it last Frame Descriptor? */
|
|
break;
|
|
|
|
assert(len == 0);
|
|
}
|
|
|
|
assert(len == 0);
|
|
|
|
s->scb_status |= SCB_STATUS_FR; /* set "RU finished receiving frame" bit. */
|
|
update_scb_status(s);
|
|
|
|
/* send IRQ that we received data */
|
|
qemu_set_irq(s->irq, 1);
|
|
/* s->send_irq = 1; */
|
|
|
|
if (0) {
|
|
DBG(printf("Checking:\n"));
|
|
rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */
|
|
DBG(printf("Next Receive: rfd is %08x\n", rfd_p));
|
|
rfd_p = get_uint32(rfd_p + 4); /* get Next Receive Frame Descriptor */
|
|
DBG(printf("Next Receive: rfd is %08x\n", rfd_p));
|
|
/* get first Receive Buffer Descriptor Address */
|
|
rbd = get_uint32(rfd_p + 8);
|
|
DBG(printf("Next Receive: rbd is %08x\n", rbd));
|
|
}
|
|
|
|
return sz;
|
|
}
|
|
|
|
|
|
const VMStateDescription vmstate_i82596 = {
|
|
.name = "i82596",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT16(lnkst, I82596State),
|
|
VMSTATE_TIMER_PTR(flush_queue_timer, I82596State),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info)
|
|
{
|
|
if (s->conf.macaddr.a[0] == 0) {
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
}
|
|
s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)),
|
|
dev->id, s);
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
|
|
|
|
if (USE_TIMER) {
|
|
s->flush_queue_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
|
i82596_flush_queue_timer, s);
|
|
}
|
|
s->lnkst = 0x8000; /* initial link state: up */
|
|
}
|