Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-Id: <20200316172155.971-15-alex.bennee@linaro.org>
150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/*
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* MIPS gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/gdbstub.h"
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int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
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}
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if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
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switch (n) {
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case 70:
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return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
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case 71:
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return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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return gdb_get_regl(mem_buf,
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env->active_fpu.fpr[n - 38].d);
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} else {
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return gdb_get_regl(mem_buf,
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env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
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}
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}
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}
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switch (n) {
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case 32:
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return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
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case 33:
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return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
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case 34:
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return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
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case 35:
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return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
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case 36:
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return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
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case 37:
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return gdb_get_regl(mem_buf, env->active_tc.PC |
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!!(env->hflags & MIPS_HFLAG_M16));
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case 72:
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return gdb_get_regl(mem_buf, 0); /* fp */
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case 89:
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return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
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default:
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if (n > 89) {
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return 0;
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}
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/* 16 embedded regs. */
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return gdb_get_regl(mem_buf, 0);
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}
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return 0;
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}
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int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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target_ulong tmp;
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tmp = ldtul_p(mem_buf);
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if (n < 32) {
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env->active_tc.gpr[n] = tmp;
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return sizeof(target_ulong);
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}
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if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
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switch (n) {
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case 70:
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env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) |
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(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
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restore_fp_status(env);
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break;
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case 71:
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/* FIR is read-only. Ignore writes. */
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break;
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default:
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if (env->CP0_Status & (1 << CP0St_FR)) {
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env->active_fpu.fpr[n - 38].d = tmp;
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} else {
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env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
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}
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break;
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}
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return sizeof(target_ulong);
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}
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switch (n) {
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case 32:
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#ifndef CONFIG_USER_ONLY
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cpu_mips_store_status(env, tmp);
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#endif
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break;
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case 33:
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env->active_tc.LO[0] = tmp;
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break;
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case 34:
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env->active_tc.HI[0] = tmp;
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break;
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case 35:
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env->CP0_BadVAddr = tmp;
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break;
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case 36:
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#ifndef CONFIG_USER_ONLY
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cpu_mips_store_cause(env, tmp);
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#endif
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break;
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case 37:
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env->active_tc.PC = tmp & ~(target_ulong)1;
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if (tmp & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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break;
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case 72: /* fp, ignored */
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break;
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default:
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if (n > 89) {
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return 0;
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}
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/* Other registers are readonly. Ignore writes. */
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break;
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}
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return sizeof(target_ulong);
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}
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