On reboot, all memory that was previously added using object_add and device_add is placed in this DIMM area. The new SPAPR_LMB_FLAGS_HOTREMOVABLE flag helps Linux to put this memory in the correct memory zone, so no unmovable allocations are made there, allowing the object to be easily hot-removed by device_del and object_del. This new flag was accepted in Power Architecture documentation. Signed-off-by: Leonardo Bras <leobras.c@gmail.com> Reviewed-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20200511200201.58537-1-leobras.c@gmail.com> [dwg: Fixed syntax error spotted by Cédric Le Goater] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
1431 lines
46 KiB
C
1431 lines
46 KiB
C
/*
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* PowerPC exception emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "internal.h"
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#include "helper_regs.h"
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/* #define DEBUG_OP */
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/* #define DEBUG_SOFTWARE_TLB */
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/* #define DEBUG_EXCEPTIONS */
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#ifdef DEBUG_EXCEPTIONS
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# define LOG_EXCP(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_EXCP(...) do { } while (0)
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#endif
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/*****************************************************************************/
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/* Exception processing */
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#if defined(CONFIG_USER_ONLY)
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void ppc_cpu_do_interrupt(CPUState *cs)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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cs->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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}
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static void ppc_hw_interrupt(CPUPPCState *env)
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{
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CPUState *cs = env_cpu(env);
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cs->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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}
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#else /* defined(CONFIG_USER_ONLY) */
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static inline void dump_syscall(CPUPPCState *env)
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{
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qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
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" r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
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" r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64
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" nip=" TARGET_FMT_lx "\n",
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ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
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ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
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ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
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ppc_dump_gpr(env, 8), env->nip);
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}
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static inline void dump_syscall_vectored(CPUPPCState *env)
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{
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qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
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" r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
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" r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64
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" nip=" TARGET_FMT_lx "\n",
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ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
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ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
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ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
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ppc_dump_gpr(env, 8), env->nip);
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}
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static inline void dump_hcall(CPUPPCState *env)
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{
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qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64
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" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
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" r7=%016" PRIx64 " r8=%016" PRIx64 " r9=%016" PRIx64
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" r10=%016" PRIx64 " r11=%016" PRIx64 " r12=%016" PRIx64
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" nip=" TARGET_FMT_lx "\n",
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ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
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ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6),
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ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
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ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
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ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
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env->nip);
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}
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static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
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target_ulong *msr)
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{
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/* We no longer are in a PM state */
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env->resume_as_sreset = false;
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/* Pretend to be returning from doze always as we don't lose state */
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*msr |= SRR1_WS_NOLOSS;
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/* Machine checks are sent normally */
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if (excp == POWERPC_EXCP_MCHECK) {
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return excp;
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}
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switch (excp) {
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case POWERPC_EXCP_RESET:
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*msr |= SRR1_WAKERESET;
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break;
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case POWERPC_EXCP_EXTERNAL:
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*msr |= SRR1_WAKEEE;
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break;
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case POWERPC_EXCP_DECR:
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*msr |= SRR1_WAKEDEC;
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break;
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case POWERPC_EXCP_SDOOR:
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*msr |= SRR1_WAKEDBELL;
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break;
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case POWERPC_EXCP_SDOOR_HV:
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*msr |= SRR1_WAKEHDBELL;
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break;
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case POWERPC_EXCP_HV_MAINT:
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*msr |= SRR1_WAKEHMI;
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break;
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case POWERPC_EXCP_HVIRT:
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*msr |= SRR1_WAKEHVI;
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break;
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default:
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cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
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excp);
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}
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return POWERPC_EXCP_RESET;
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}
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static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail)
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{
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uint64_t offset = 0;
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switch (ail) {
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case AIL_NONE:
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break;
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case AIL_0001_8000:
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offset = 0x18000;
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break;
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case AIL_C000_0000_0000_4000:
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offset = 0xc000000000004000ull;
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break;
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default:
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cpu_abort(cs, "Invalid AIL combination %d\n", ail);
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break;
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}
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return offset;
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}
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static inline void powerpc_set_excp_state(PowerPCCPU *cpu,
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target_ulong vector, target_ulong msr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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/*
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* We don't use hreg_store_msr here as already have treated any
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* special case that could occur. Just store MSR and update hflags
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*
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* Note: We *MUST* not use hreg_store_msr() as-is anyway because it
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* will prevent setting of the HV bit which some exceptions might need
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* to do.
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*/
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env->msr = msr & env->msr_mask;
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hreg_compute_hflags(env);
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env->nip = vector;
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/* Reset exception state */
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cs->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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/* Reset the reservation */
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env->reserve_addr = -1;
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/*
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* Any interrupt is context synchronizing, check if TCG TLB needs
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* a delayed flush on ppc64
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*/
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check_tlb_flush(env, false);
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}
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/*
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* Note that this function should be greatly optimized when called
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* with a constant excp, from ppc_hw_interrupt
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*/
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static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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target_ulong msr, new_msr, vector;
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int srr0, srr1, asrr0, asrr1, lev = -1, ail;
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bool lpes0;
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qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
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" => %08x (%02x)\n", env->nip, excp, env->error_code);
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/* new srr1 value excluding must-be-zero bits */
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if (excp_model == POWERPC_EXCP_BOOKE) {
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msr = env->msr;
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} else {
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msr = env->msr & ~0x783f0000ULL;
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}
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/*
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* new interrupt handler msr preserves existing HV and ME unless
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* explicitly overriden
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*/
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new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
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/* target registers */
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srr0 = SPR_SRR0;
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srr1 = SPR_SRR1;
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asrr0 = -1;
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asrr1 = -1;
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/*
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* check for special resume at 0x100 from doze/nap/sleep/winkle on
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* P7/P8/P9
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*/
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if (env->resume_as_sreset) {
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excp = powerpc_reset_wakeup(cs, env, excp, &msr);
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}
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/*
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* Exception targetting modifiers
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*
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* LPES0 is supported on POWER7/8/9
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* LPES1 is not supported (old iSeries mode)
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*
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* On anything else, we behave as if LPES0 is 1
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* (externals don't alter MSR:HV)
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*
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* AIL is initialized here but can be cleared by
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* selected exceptions
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*/
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#if defined(TARGET_PPC64)
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if (excp_model == POWERPC_EXCP_POWER7 ||
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excp_model == POWERPC_EXCP_POWER8 ||
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excp_model == POWERPC_EXCP_POWER9) {
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lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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if (excp_model != POWERPC_EXCP_POWER7) {
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ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
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} else {
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ail = 0;
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}
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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lpes0 = true;
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ail = 0;
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}
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/*
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* Hypervisor emulation assistance interrupt only exists on server
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* arch 2.05 server or later. We also don't want to generate it if
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* we don't have HVB in msr_mask (PAPR mode).
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*/
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if (excp == POWERPC_EXCP_HV_EMU
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#if defined(TARGET_PPC64)
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&& !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
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#endif /* defined(TARGET_PPC64) */
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) {
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excp = POWERPC_EXCP_PROGRAM;
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}
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switch (excp) {
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case POWERPC_EXCP_NONE:
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/* Should never happen */
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return;
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case POWERPC_EXCP_CRITICAL: /* Critical input */
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switch (excp_model) {
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case POWERPC_EXCP_40x:
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srr0 = SPR_40x_SRR2;
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srr1 = SPR_40x_SRR3;
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break;
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case POWERPC_EXCP_BOOKE:
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srr0 = SPR_BOOKE_CSRR0;
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srr1 = SPR_BOOKE_CSRR1;
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break;
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case POWERPC_EXCP_G2:
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break;
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default:
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goto excp_invalid;
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}
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break;
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case POWERPC_EXCP_MCHECK: /* Machine check exception */
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if (msr_me == 0) {
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/*
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* Machine check exception is not enabled. Enter
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* checkstop state.
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*/
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fprintf(stderr, "Machine check while not allowed. "
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"Entering checkstop state\n");
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if (qemu_log_separate()) {
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qemu_log("Machine check while not allowed. "
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"Entering checkstop state\n");
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}
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cs->halted = 1;
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cpu_interrupt_exittb(cs);
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}
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if (env->msr_mask & MSR_HVB) {
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/*
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* ISA specifies HV, but can be delivered to guest with HV
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* clear (e.g., see FWNMI in PAPR).
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*/
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new_msr |= (target_ulong)MSR_HVB;
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}
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ail = 0;
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/* machine check exceptions don't have ME set */
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new_msr &= ~((target_ulong)1 << MSR_ME);
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/* XXX: should also have something loaded in DAR / DSISR */
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switch (excp_model) {
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case POWERPC_EXCP_40x:
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srr0 = SPR_40x_SRR2;
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srr1 = SPR_40x_SRR3;
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break;
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case POWERPC_EXCP_BOOKE:
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/* FIXME: choose one or the other based on CPU type */
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srr0 = SPR_BOOKE_MCSRR0;
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srr1 = SPR_BOOKE_MCSRR1;
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asrr0 = SPR_BOOKE_CSRR0;
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asrr1 = SPR_BOOKE_CSRR1;
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break;
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default:
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break;
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}
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break;
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case POWERPC_EXCP_DSI: /* Data storage exception */
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LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
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"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
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break;
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case POWERPC_EXCP_ISI: /* Instruction storage exception */
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LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
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"\n", msr, env->nip);
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msr |= env->error_code;
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break;
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case POWERPC_EXCP_EXTERNAL: /* External input */
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cs = CPU(cpu);
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if (!lpes0) {
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new_msr |= (target_ulong)MSR_HVB;
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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srr0 = SPR_HSRR0;
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srr1 = SPR_HSRR1;
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}
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if (env->mpic_proxy) {
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/* IACK the IRQ on delivery */
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env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
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}
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break;
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case POWERPC_EXCP_ALIGN: /* Alignment exception */
|
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/* Get rS/rD and rA from faulting opcode */
|
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/*
|
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* Note: the opcode fields will not be set properly for a
|
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* direct store load/store, but nobody cares as nobody
|
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* actually uses direct store segments.
|
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*/
|
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env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
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break;
|
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case POWERPC_EXCP_PROGRAM: /* Program exception */
|
|
switch (env->error_code & ~0xF) {
|
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case POWERPC_EXCP_FP:
|
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if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
|
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LOG_EXCP("Ignore floating point exception\n");
|
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cs->exception_index = POWERPC_EXCP_NONE;
|
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env->error_code = 0;
|
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return;
|
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}
|
|
|
|
/*
|
|
* FP exceptions always have NIP pointing to the faulting
|
|
* instruction, so always use store_next and claim we are
|
|
* precise in the MSR.
|
|
*/
|
|
msr |= 0x00100000;
|
|
env->spr[SPR_BOOKE_ESR] = ESR_FP;
|
|
break;
|
|
case POWERPC_EXCP_INVAL:
|
|
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
|
|
msr |= 0x00080000;
|
|
env->spr[SPR_BOOKE_ESR] = ESR_PIL;
|
|
break;
|
|
case POWERPC_EXCP_PRIV:
|
|
msr |= 0x00040000;
|
|
env->spr[SPR_BOOKE_ESR] = ESR_PPR;
|
|
break;
|
|
case POWERPC_EXCP_TRAP:
|
|
msr |= 0x00020000;
|
|
env->spr[SPR_BOOKE_ESR] = ESR_PTR;
|
|
break;
|
|
default:
|
|
/* Should never occur */
|
|
cpu_abort(cs, "Invalid program exception %d. Aborting\n",
|
|
env->error_code);
|
|
break;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_SYSCALL: /* System call exception */
|
|
lev = env->error_code;
|
|
|
|
if ((lev == 1) && cpu->vhyp) {
|
|
dump_hcall(env);
|
|
} else {
|
|
dump_syscall(env);
|
|
}
|
|
|
|
/*
|
|
* We need to correct the NIP which in this case is supposed
|
|
* to point to the next instruction
|
|
*/
|
|
env->nip += 4;
|
|
|
|
/* "PAPR mode" built-in hypercall emulation */
|
|
if ((lev == 1) && cpu->vhyp) {
|
|
PPCVirtualHypervisorClass *vhc =
|
|
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
|
vhc->hypercall(cpu->vhyp, cpu);
|
|
return;
|
|
}
|
|
if (lev == 1) {
|
|
new_msr |= (target_ulong)MSR_HVB;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
|
|
lev = env->error_code;
|
|
dump_syscall_vectored(env);
|
|
env->nip += 4;
|
|
new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
|
|
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
break;
|
|
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
|
|
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
|
|
case POWERPC_EXCP_DECR: /* Decrementer exception */
|
|
break;
|
|
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
|
|
/* FIT on 4xx */
|
|
LOG_EXCP("FIT exception\n");
|
|
break;
|
|
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
|
|
LOG_EXCP("WDT exception\n");
|
|
switch (excp_model) {
|
|
case POWERPC_EXCP_BOOKE:
|
|
srr0 = SPR_BOOKE_CSRR0;
|
|
srr1 = SPR_BOOKE_CSRR1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_DTLB: /* Data TLB error */
|
|
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
|
|
break;
|
|
case POWERPC_EXCP_DEBUG: /* Debug interrupt */
|
|
if (env->flags & POWERPC_FLAG_DE) {
|
|
/* FIXME: choose one or the other based on CPU type */
|
|
srr0 = SPR_BOOKE_DSRR0;
|
|
srr1 = SPR_BOOKE_DSRR1;
|
|
asrr0 = SPR_BOOKE_CSRR0;
|
|
asrr1 = SPR_BOOKE_CSRR1;
|
|
/* DBSR already modified by caller */
|
|
} else {
|
|
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
|
|
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
|
|
break;
|
|
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Embedded floating point data exception "
|
|
"is not implemented yet !\n");
|
|
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
|
|
break;
|
|
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Embedded floating point round exception "
|
|
"is not implemented yet !\n");
|
|
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
|
|
break;
|
|
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs,
|
|
"Performance counter exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
|
|
break;
|
|
case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
|
|
srr0 = SPR_BOOKE_CSRR0;
|
|
srr1 = SPR_BOOKE_CSRR1;
|
|
break;
|
|
case POWERPC_EXCP_RESET: /* System reset exception */
|
|
/* A power-saving exception sets ME, otherwise it is unchanged */
|
|
if (msr_pow) {
|
|
/* indicate that we resumed from power save mode */
|
|
msr |= 0x10000;
|
|
new_msr |= ((target_ulong)1 << MSR_ME);
|
|
}
|
|
if (env->msr_mask & MSR_HVB) {
|
|
/*
|
|
* ISA specifies HV, but can be delivered to guest with HV
|
|
* clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
|
|
*/
|
|
new_msr |= (target_ulong)MSR_HVB;
|
|
} else {
|
|
if (msr_pow) {
|
|
cpu_abort(cs, "Trying to deliver power-saving system reset "
|
|
"exception %d with no HV support\n", excp);
|
|
}
|
|
}
|
|
ail = 0;
|
|
break;
|
|
case POWERPC_EXCP_DSEG: /* Data segment exception */
|
|
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
|
|
case POWERPC_EXCP_TRACE: /* Trace exception */
|
|
break;
|
|
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
|
|
msr |= env->error_code;
|
|
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
|
|
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
|
|
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
|
|
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
|
|
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
|
|
case POWERPC_EXCP_HV_EMU:
|
|
case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
|
|
srr0 = SPR_HSRR0;
|
|
srr1 = SPR_HSRR1;
|
|
new_msr |= (target_ulong)MSR_HVB;
|
|
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
break;
|
|
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
|
|
case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
|
|
case POWERPC_EXCP_FU: /* Facility unavailable exception */
|
|
#ifdef TARGET_PPC64
|
|
env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
|
|
#endif
|
|
break;
|
|
case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
|
|
#ifdef TARGET_PPC64
|
|
env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
|
|
srr0 = SPR_HSRR0;
|
|
srr1 = SPR_HSRR1;
|
|
new_msr |= (target_ulong)MSR_HVB;
|
|
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
|
|
#endif
|
|
break;
|
|
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
|
|
LOG_EXCP("PIT exception\n");
|
|
break;
|
|
case POWERPC_EXCP_IO: /* IO error exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_RUNM: /* Run mode exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_EMUL: /* Emulation trap exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "602 emulation trap exception "
|
|
"is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
|
|
switch (excp_model) {
|
|
case POWERPC_EXCP_602:
|
|
case POWERPC_EXCP_603:
|
|
case POWERPC_EXCP_603E:
|
|
case POWERPC_EXCP_G2:
|
|
goto tlb_miss_tgpr;
|
|
case POWERPC_EXCP_7x5:
|
|
goto tlb_miss;
|
|
case POWERPC_EXCP_74xx:
|
|
goto tlb_miss_74xx;
|
|
default:
|
|
cpu_abort(cs, "Invalid instruction TLB miss exception\n");
|
|
break;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
|
|
switch (excp_model) {
|
|
case POWERPC_EXCP_602:
|
|
case POWERPC_EXCP_603:
|
|
case POWERPC_EXCP_603E:
|
|
case POWERPC_EXCP_G2:
|
|
goto tlb_miss_tgpr;
|
|
case POWERPC_EXCP_7x5:
|
|
goto tlb_miss;
|
|
case POWERPC_EXCP_74xx:
|
|
goto tlb_miss_74xx;
|
|
default:
|
|
cpu_abort(cs, "Invalid data load TLB miss exception\n");
|
|
break;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
|
|
switch (excp_model) {
|
|
case POWERPC_EXCP_602:
|
|
case POWERPC_EXCP_603:
|
|
case POWERPC_EXCP_603E:
|
|
case POWERPC_EXCP_G2:
|
|
tlb_miss_tgpr:
|
|
/* Swap temporary saved registers with GPRs */
|
|
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
|
|
new_msr |= (target_ulong)1 << MSR_TGPR;
|
|
hreg_swap_gpr_tgpr(env);
|
|
}
|
|
goto tlb_miss;
|
|
case POWERPC_EXCP_7x5:
|
|
tlb_miss:
|
|
#if defined(DEBUG_SOFTWARE_TLB)
|
|
if (qemu_log_enabled()) {
|
|
const char *es;
|
|
target_ulong *miss, *cmp;
|
|
int en;
|
|
|
|
if (excp == POWERPC_EXCP_IFTLB) {
|
|
es = "I";
|
|
en = 'I';
|
|
miss = &env->spr[SPR_IMISS];
|
|
cmp = &env->spr[SPR_ICMP];
|
|
} else {
|
|
if (excp == POWERPC_EXCP_DLTLB) {
|
|
es = "DL";
|
|
} else {
|
|
es = "DS";
|
|
}
|
|
en = 'D';
|
|
miss = &env->spr[SPR_DMISS];
|
|
cmp = &env->spr[SPR_DCMP];
|
|
}
|
|
qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
|
|
TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
|
|
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
|
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
|
|
env->error_code);
|
|
}
|
|
#endif
|
|
msr |= env->crf[0] << 28;
|
|
msr |= env->error_code; /* key, D/I, S/L bits */
|
|
/* Set way using a LRU mechanism */
|
|
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
|
|
break;
|
|
case POWERPC_EXCP_74xx:
|
|
tlb_miss_74xx:
|
|
#if defined(DEBUG_SOFTWARE_TLB)
|
|
if (qemu_log_enabled()) {
|
|
const char *es;
|
|
target_ulong *miss, *cmp;
|
|
int en;
|
|
|
|
if (excp == POWERPC_EXCP_IFTLB) {
|
|
es = "I";
|
|
en = 'I';
|
|
miss = &env->spr[SPR_TLBMISS];
|
|
cmp = &env->spr[SPR_PTEHI];
|
|
} else {
|
|
if (excp == POWERPC_EXCP_DLTLB) {
|
|
es = "DL";
|
|
} else {
|
|
es = "DS";
|
|
}
|
|
en = 'D';
|
|
miss = &env->spr[SPR_TLBMISS];
|
|
cmp = &env->spr[SPR_PTEHI];
|
|
}
|
|
qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
|
|
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
|
env->error_code);
|
|
}
|
|
#endif
|
|
msr |= env->error_code; /* key bit */
|
|
break;
|
|
default:
|
|
cpu_abort(cs, "Invalid data store TLB miss exception\n");
|
|
break;
|
|
}
|
|
break;
|
|
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Floating point assist exception "
|
|
"is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_DABR: /* Data address breakpoint */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "DABR exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "IABR exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_SMI: /* System management interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "SMI exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_THERM: /* Thermal interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Thermal management exception "
|
|
"is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs,
|
|
"Performance counter exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_VPUA: /* Vector assist exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_SOFTP: /* Soft patch exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs,
|
|
"970 soft-patch exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_MAINT: /* Maintenance exception */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs,
|
|
"970 maintenance exception is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Maskable external exception "
|
|
"is not implemented yet !\n");
|
|
break;
|
|
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
|
|
/* XXX: TODO */
|
|
cpu_abort(cs, "Non maskable external exception "
|
|
"is not implemented yet !\n");
|
|
break;
|
|
default:
|
|
excp_invalid:
|
|
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
|
|
break;
|
|
}
|
|
|
|
/* Sanity check */
|
|
if (!(env->msr_mask & MSR_HVB)) {
|
|
if (new_msr & MSR_HVB) {
|
|
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
|
|
"no HV support\n", excp);
|
|
}
|
|
if (srr0 == SPR_HSRR0) {
|
|
cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
|
|
"no HV support\n", excp);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Sort out endianness of interrupt, this differs depending on the
|
|
* CPU, the HV mode, etc...
|
|
*/
|
|
#ifdef TARGET_PPC64
|
|
if (excp_model == POWERPC_EXCP_POWER7) {
|
|
if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
} else if (excp_model == POWERPC_EXCP_POWER8) {
|
|
if (new_msr & MSR_HVB) {
|
|
if (env->spr[SPR_HID0] & HID0_HILE) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
} else if (excp_model == POWERPC_EXCP_POWER9) {
|
|
if (new_msr & MSR_HVB) {
|
|
if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
} else if (msr_ile) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
#else
|
|
if (msr_ile) {
|
|
new_msr |= (target_ulong)1 << MSR_LE;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* AIL only works if there is no HV transition and we are running
|
|
* with translations enabled
|
|
*/
|
|
if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
|
|
((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
|
|
ail = 0;
|
|
}
|
|
|
|
vector = env->excp_vectors[excp];
|
|
if (vector == (target_ulong)-1ULL) {
|
|
cpu_abort(cs, "Raised an exception without defined vector %d\n",
|
|
excp);
|
|
}
|
|
|
|
vector |= env->excp_prefix;
|
|
|
|
/* If any alternate SRR register are defined, duplicate saved values */
|
|
if (asrr0 != -1) {
|
|
env->spr[asrr0] = env->nip;
|
|
}
|
|
if (asrr1 != -1) {
|
|
env->spr[asrr1] = msr;
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
if (excp_model == POWERPC_EXCP_BOOKE) {
|
|
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
|
|
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
|
|
new_msr |= (target_ulong)1 << MSR_CM;
|
|
} else {
|
|
vector = (uint32_t)vector;
|
|
}
|
|
} else {
|
|
if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
|
|
vector = (uint32_t)vector;
|
|
} else {
|
|
new_msr |= (target_ulong)1 << MSR_SF;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
|
|
/* Save PC */
|
|
env->spr[srr0] = env->nip;
|
|
|
|
/* Save MSR */
|
|
env->spr[srr1] = msr;
|
|
|
|
/* Handle AIL */
|
|
if (ail) {
|
|
new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
|
|
vector |= ppc_excp_vector_offset(cs, ail);
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
} else {
|
|
/* scv AIL is a little different */
|
|
if (ail) {
|
|
new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
|
|
}
|
|
if (ail == AIL_C000_0000_0000_4000) {
|
|
vector |= 0xc000000000003000ull;
|
|
} else {
|
|
vector |= 0x0000000000017000ull;
|
|
}
|
|
vector += lev * 0x20;
|
|
|
|
env->lr = env->nip;
|
|
env->ctr = msr;
|
|
#endif
|
|
}
|
|
|
|
powerpc_set_excp_state(cpu, vector, new_msr);
|
|
}
|
|
|
|
void ppc_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
powerpc_excp(cpu, env->excp_model, cs->exception_index);
|
|
}
|
|
|
|
static void ppc_hw_interrupt(CPUPPCState *env)
|
|
{
|
|
PowerPCCPU *cpu = env_archcpu(env);
|
|
bool async_deliver;
|
|
|
|
/* External reset */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
|
|
return;
|
|
}
|
|
/* Machine check exception */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
|
|
return;
|
|
}
|
|
#if 0 /* TODO */
|
|
/* External debug exception */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* For interrupts that gate on MSR:EE, we need to do something a
|
|
* bit more subtle, as we need to let them through even when EE is
|
|
* clear when coming out of some power management states (in order
|
|
* for them to become a 0x100).
|
|
*/
|
|
async_deliver = (msr_ee != 0) || env->resume_as_sreset;
|
|
|
|
/* Hypervisor decrementer exception */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
|
|
/* LPCR will be clear when not supported so this will work */
|
|
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
|
|
if ((async_deliver || msr_hv == 0) && hdice) {
|
|
/* HDEC clears on delivery */
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Hypervisor virtualization interrupt */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
|
|
/* LPCR will be clear when not supported so this will work */
|
|
bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
|
|
if ((async_deliver || msr_hv == 0) && hvice) {
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HVIRT);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* External interrupt can ignore MSR:EE under some circumstances */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
|
|
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
|
|
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
|
|
/* HEIC blocks delivery to the hypervisor */
|
|
if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
|
|
(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
|
|
return;
|
|
}
|
|
}
|
|
if (msr_ce != 0) {
|
|
/* External critical interrupt */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
|
|
return;
|
|
}
|
|
}
|
|
if (async_deliver != 0) {
|
|
/* Watchdog timer on embedded PowerPC */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
|
|
return;
|
|
}
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
|
|
return;
|
|
}
|
|
/* Fixed interval timer on embedded PowerPC */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
|
|
return;
|
|
}
|
|
/* Programmable interval timer on embedded PowerPC */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
|
|
return;
|
|
}
|
|
/* Decrementer exception */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
|
|
if (ppc_decr_clear_on_delivery(env)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
|
}
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
|
|
return;
|
|
}
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
|
if (is_book3s_arch2x(env)) {
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR);
|
|
} else {
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
|
|
}
|
|
return;
|
|
}
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV);
|
|
return;
|
|
}
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
|
|
return;
|
|
}
|
|
/* Thermal interrupt */
|
|
if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (env->resume_as_sreset) {
|
|
/*
|
|
* This is a bug ! It means that has_work took us out of halt without
|
|
* anything to deliver while in a PM state that requires getting
|
|
* out via a 0x100
|
|
*
|
|
* This means we will incorrectly execute past the power management
|
|
* instruction instead of triggering a reset.
|
|
*
|
|
* It generally means a discrepancy between the wakup conditions in the
|
|
* processor has_work implementation and the logic in this function.
|
|
*/
|
|
cpu_abort(env_cpu(env),
|
|
"Wakeup from PM state but interrupt Undelivered");
|
|
}
|
|
}
|
|
|
|
void ppc_cpu_do_system_reset(CPUState *cs)
|
|
{
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
|
|
}
|
|
|
|
void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
|
|
{
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *env = &cpu->env;
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
target_ulong msr = 0;
|
|
|
|
/*
|
|
* Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already
|
|
* been set by KVM.
|
|
*/
|
|
msr = (1ULL << MSR_ME);
|
|
msr |= env->msr & (1ULL << MSR_SF);
|
|
if (!(*pcc->interrupts_big_endian)(cpu)) {
|
|
msr |= (1ULL << MSR_LE);
|
|
}
|
|
|
|
powerpc_set_excp_state(cpu, vector, msr);
|
|
}
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
ppc_hw_interrupt(env);
|
|
if (env->pending_interrupts == 0) {
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
#if defined(DEBUG_OP)
|
|
static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
|
|
{
|
|
qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
|
|
TARGET_FMT_lx "\n", RA, msr);
|
|
}
|
|
#endif
|
|
|
|
/*****************************************************************************/
|
|
/* Exceptions processing helpers */
|
|
|
|
void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
|
|
uint32_t error_code, uintptr_t raddr)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
cs->exception_index = exception;
|
|
env->error_code = error_code;
|
|
cpu_loop_exit_restore(cs, raddr);
|
|
}
|
|
|
|
void raise_exception_err(CPUPPCState *env, uint32_t exception,
|
|
uint32_t error_code)
|
|
{
|
|
raise_exception_err_ra(env, exception, error_code, 0);
|
|
}
|
|
|
|
void raise_exception(CPUPPCState *env, uint32_t exception)
|
|
{
|
|
raise_exception_err_ra(env, exception, 0, 0);
|
|
}
|
|
|
|
void raise_exception_ra(CPUPPCState *env, uint32_t exception,
|
|
uintptr_t raddr)
|
|
{
|
|
raise_exception_err_ra(env, exception, 0, raddr);
|
|
}
|
|
|
|
void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
|
|
uint32_t error_code)
|
|
{
|
|
raise_exception_err_ra(env, exception, error_code, 0);
|
|
}
|
|
|
|
void helper_raise_exception(CPUPPCState *env, uint32_t exception)
|
|
{
|
|
raise_exception_err_ra(env, exception, 0, 0);
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
void helper_store_msr(CPUPPCState *env, target_ulong val)
|
|
{
|
|
uint32_t excp = hreg_store_msr(env, val, 0);
|
|
|
|
if (excp != 0) {
|
|
CPUState *cs = env_cpu(env);
|
|
cpu_interrupt_exittb(cs);
|
|
raise_exception(env, excp);
|
|
}
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
|
|
{
|
|
CPUState *cs;
|
|
|
|
cs = env_cpu(env);
|
|
cs->halted = 1;
|
|
|
|
/*
|
|
* The architecture specifies that HDEC interrupts are discarded
|
|
* in PM states
|
|
*/
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
|
|
|
/* Condition for waking up at 0x100 */
|
|
env->resume_as_sreset = (insn != PPC_PM_STOP) ||
|
|
(env->spr[SPR_PSSCR] & PSSCR_EC);
|
|
}
|
|
#endif /* defined(TARGET_PPC64) */
|
|
|
|
static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
/* MSR:POW cannot be set by any form of rfi */
|
|
msr &= ~(1ULL << MSR_POW);
|
|
|
|
#if defined(TARGET_PPC64)
|
|
/* Switching to 32-bit ? Crop the nip */
|
|
if (!msr_is_64bit(env, msr)) {
|
|
nip = (uint32_t)nip;
|
|
}
|
|
#else
|
|
nip = (uint32_t)nip;
|
|
#endif
|
|
/* XXX: beware: this is false if VLE is supported */
|
|
env->nip = nip & ~((target_ulong)0x00000003);
|
|
hreg_store_msr(env, msr, 1);
|
|
#if defined(DEBUG_OP)
|
|
cpu_dump_rfi(env->nip, env->msr);
|
|
#endif
|
|
/*
|
|
* No need to raise an exception here, as rfi is always the last
|
|
* insn of a TB
|
|
*/
|
|
cpu_interrupt_exittb(cs);
|
|
/* Reset the reservation */
|
|
env->reserve_addr = -1;
|
|
|
|
/* Context synchronizing: check if TCG TLB needs flush */
|
|
check_tlb_flush(env, false);
|
|
}
|
|
|
|
void helper_rfi(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
|
|
}
|
|
|
|
#define MSR_BOOK3S_MASK
|
|
#if defined(TARGET_PPC64)
|
|
void helper_rfid(CPUPPCState *env)
|
|
{
|
|
/*
|
|
* The architeture defines a number of rules for which bits can
|
|
* change but in practice, we handle this in hreg_store_msr()
|
|
* which will be called by do_rfi(), so there is no need to filter
|
|
* here
|
|
*/
|
|
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
|
|
}
|
|
|
|
void helper_rfscv(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->lr, env->ctr);
|
|
}
|
|
|
|
void helper_hrfid(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
|
|
}
|
|
#endif
|
|
|
|
/*****************************************************************************/
|
|
/* Embedded PowerPC specific helpers */
|
|
void helper_40x_rfci(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
|
|
}
|
|
|
|
void helper_rfci(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
|
|
}
|
|
|
|
void helper_rfdi(CPUPPCState *env)
|
|
{
|
|
/* FIXME: choose CSRR1 or DSRR1 based on cpu type */
|
|
do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
|
|
}
|
|
|
|
void helper_rfmci(CPUPPCState *env)
|
|
{
|
|
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
|
|
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
|
|
}
|
|
#endif
|
|
|
|
void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
|
|
uint32_t flags)
|
|
{
|
|
if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
|
|
((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
|
|
((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
|
|
((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
|
|
((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
|
|
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
|
|
POWERPC_EXCP_TRAP, GETPC());
|
|
}
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
|
|
uint32_t flags)
|
|
{
|
|
if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
|
|
((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
|
|
((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
|
|
((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
|
|
((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
|
|
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
|
|
POWERPC_EXCP_TRAP, GETPC());
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
/*****************************************************************************/
|
|
/* PowerPC 601 specific instructions (POWER bridge) */
|
|
|
|
void helper_rfsvc(CPUPPCState *env)
|
|
{
|
|
do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
|
|
}
|
|
|
|
/* Embedded.Processor Control */
|
|
static int dbell2irq(target_ulong rb)
|
|
{
|
|
int msg = rb & DBELL_TYPE_MASK;
|
|
int irq = -1;
|
|
|
|
switch (msg) {
|
|
case DBELL_TYPE_DBELL:
|
|
irq = PPC_INTERRUPT_DOORBELL;
|
|
break;
|
|
case DBELL_TYPE_DBELL_CRIT:
|
|
irq = PPC_INTERRUPT_CDOORBELL;
|
|
break;
|
|
case DBELL_TYPE_G_DBELL:
|
|
case DBELL_TYPE_G_DBELL_CRIT:
|
|
case DBELL_TYPE_G_DBELL_MC:
|
|
/* XXX implement */
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return irq;
|
|
}
|
|
|
|
void helper_msgclr(CPUPPCState *env, target_ulong rb)
|
|
{
|
|
int irq = dbell2irq(rb);
|
|
|
|
if (irq < 0) {
|
|
return;
|
|
}
|
|
|
|
env->pending_interrupts &= ~(1 << irq);
|
|
}
|
|
|
|
void helper_msgsnd(target_ulong rb)
|
|
{
|
|
int irq = dbell2irq(rb);
|
|
int pir = rb & DBELL_PIRTAG_MASK;
|
|
CPUState *cs;
|
|
|
|
if (irq < 0) {
|
|
return;
|
|
}
|
|
|
|
qemu_mutex_lock_iothread();
|
|
CPU_FOREACH(cs) {
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *cenv = &cpu->env;
|
|
|
|
if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
|
|
cenv->pending_interrupts |= 1 << irq;
|
|
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
|
}
|
|
}
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
|
|
/* Server Processor Control */
|
|
|
|
static bool dbell_type_server(target_ulong rb)
|
|
{
|
|
/*
|
|
* A Directed Hypervisor Doorbell message is sent only if the
|
|
* message type is 5. All other types are reserved and the
|
|
* instruction is a no-op
|
|
*/
|
|
return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER;
|
|
}
|
|
|
|
void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
|
|
{
|
|
if (!dbell_type_server(rb)) {
|
|
return;
|
|
}
|
|
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL);
|
|
}
|
|
|
|
static void book3s_msgsnd_common(int pir, int irq)
|
|
{
|
|
CPUState *cs;
|
|
|
|
qemu_mutex_lock_iothread();
|
|
CPU_FOREACH(cs) {
|
|
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
|
CPUPPCState *cenv = &cpu->env;
|
|
|
|
/* TODO: broadcast message to all threads of the same processor */
|
|
if (cenv->spr_cb[SPR_PIR].default_value == pir) {
|
|
cenv->pending_interrupts |= 1 << irq;
|
|
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
|
}
|
|
}
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
|
|
void helper_book3s_msgsnd(target_ulong rb)
|
|
{
|
|
int pir = rb & DBELL_PROCIDTAG_MASK;
|
|
|
|
if (!dbell_type_server(rb)) {
|
|
return;
|
|
}
|
|
|
|
book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL);
|
|
}
|
|
|
|
#if defined(TARGET_PPC64)
|
|
void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
|
|
{
|
|
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
|
|
|
|
if (!dbell_type_server(rb)) {
|
|
return;
|
|
}
|
|
|
|
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
|
}
|
|
|
|
/*
|
|
* sends a message to other threads that are on the same
|
|
* multi-threaded processor
|
|
*/
|
|
void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
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|
{
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|
int pir = env->spr_cb[SPR_PIR].default_value;
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|
|
|
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
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|
|
|
if (!dbell_type_server(rb)) {
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return;
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|
}
|
|
|
|
/* TODO: TCG supports only one thread */
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|
|
|
book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
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|
}
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|
#endif
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|
#endif
|
|
|
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void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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|
MMUAccessType access_type,
|
|
int mmu_idx, uintptr_t retaddr)
|
|
{
|
|
CPUPPCState *env = cs->env_ptr;
|
|
uint32_t insn;
|
|
|
|
/* Restore state and reload the insn we executed, for filling in DSISR. */
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|
cpu_restore_state(cs, retaddr, true);
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|
insn = cpu_ldl_code(env, env->nip);
|
|
|
|
cs->exception_index = POWERPC_EXCP_ALIGN;
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|
env->error_code = insn & 0x03FF0000;
|
|
cpu_loop_exit(cs);
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|
}
|