Today, when notifying a VM state change with vm_state_notify(), we pass a VMSTOP macro as the 'reason' argument. This is not ideal because the VMSTOP macros tell why qemu stopped and not exactly what the current VM state is. One example to demonstrate this problem is that vm_start() calls vm_state_notify() with reason=0, which turns out to be VMSTOP_USER. This commit fixes that by replacing the VMSTOP macros with a proper state type called RunState. Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
533 lines
15 KiB
C
533 lines
15 KiB
C
/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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#define BMDMA_PAGE_SIZE 4096
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static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
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BlockDriverCompletionFunc *dma_cb)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->unit = s->unit;
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bm->dma_cb = dma_cb;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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bm->sector_num = ide_get_sector(s);
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bm->nsector = s->nsector;
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if (bm->status & BM_STATUS_DMAING) {
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bm->dma_cb(bmdma_active_if(bm), 0);
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}
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}
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/* return 0 if buffer completed */
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static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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IDEState *s = bmdma_active_if(bm);
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struct {
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uint32_t addr;
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uint32_t size;
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} prd;
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int l, len;
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qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
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s->io_buffer_size = 0;
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for(;;) {
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if (bm->cur_prd_len == 0) {
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
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return s->io_buffer_size != 0;
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cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr);
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prd.size = le32_to_cpu(prd.size);
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len = prd.size & 0xfffe;
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if (len == 0)
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len = 0x10000;
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bm->cur_prd_len = len;
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bm->cur_prd_addr = prd.addr;
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bm->cur_prd_last = (prd.size & 0x80000000);
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}
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l = bm->cur_prd_len;
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if (l > 0) {
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qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
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bm->cur_prd_addr += l;
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bm->cur_prd_len -= l;
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s->io_buffer_size += l;
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}
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}
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return 1;
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}
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/* return 0 if buffer completed */
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static int bmdma_rw_buf(IDEDMA *dma, int is_write)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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IDEState *s = bmdma_active_if(bm);
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struct {
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uint32_t addr;
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uint32_t size;
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} prd;
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int l, len;
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for(;;) {
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l = s->io_buffer_size - s->io_buffer_index;
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if (l <= 0)
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break;
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if (bm->cur_prd_len == 0) {
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
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return 0;
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cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr);
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prd.size = le32_to_cpu(prd.size);
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len = prd.size & 0xfffe;
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if (len == 0)
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len = 0x10000;
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bm->cur_prd_len = len;
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bm->cur_prd_addr = prd.addr;
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bm->cur_prd_last = (prd.size & 0x80000000);
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}
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if (l > bm->cur_prd_len)
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l = bm->cur_prd_len;
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if (l > 0) {
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if (is_write) {
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cpu_physical_memory_write(bm->cur_prd_addr,
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s->io_buffer + s->io_buffer_index, l);
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} else {
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cpu_physical_memory_read(bm->cur_prd_addr,
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s->io_buffer + s->io_buffer_index, l);
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}
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bm->cur_prd_addr += l;
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bm->cur_prd_len -= l;
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s->io_buffer_index += l;
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}
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}
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return 1;
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}
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static int bmdma_set_unit(IDEDMA *dma, int unit)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->unit = unit;
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return 0;
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}
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static int bmdma_add_status(IDEDMA *dma, int status)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->status |= status;
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return 0;
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}
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static int bmdma_set_inactive(IDEDMA *dma)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->status &= ~BM_STATUS_DMAING;
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bm->dma_cb = NULL;
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bm->unit = -1;
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return 0;
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}
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static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
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{
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IDEState *s = bmdma_active_if(bm);
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ide_set_sector(s, bm->sector_num);
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s->io_buffer_index = 0;
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s->io_buffer_size = 0;
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s->nsector = bm->nsector;
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s->dma_cmd = dma_cmd;
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bm->cur_addr = bm->addr;
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bm->dma_cb = ide_dma_cb;
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bmdma_start_dma(&bm->dma, s, bm->dma_cb);
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}
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/* TODO This should be common IDE code */
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static void bmdma_restart_bh(void *opaque)
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{
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BMDMAState *bm = opaque;
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IDEBus *bus = bm->bus;
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int is_read;
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int error_status;
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qemu_bh_delete(bm->bh);
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bm->bh = NULL;
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if (bm->unit == (uint8_t) -1) {
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return;
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}
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is_read = !!(bus->error_status & BM_STATUS_RETRY_READ);
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/* The error status must be cleared before resubmitting the request: The
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* request may fail again, and this case can only be distinguished if the
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* called function can set a new error status. */
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error_status = bus->error_status;
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bus->error_status = 0;
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if (error_status & BM_STATUS_DMA_RETRY) {
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if (error_status & BM_STATUS_RETRY_TRIM) {
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bmdma_restart_dma(bm, IDE_DMA_TRIM);
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} else {
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bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
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}
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} else if (error_status & BM_STATUS_PIO_RETRY) {
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if (is_read) {
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ide_sector_read(bmdma_active_if(bm));
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} else {
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ide_sector_write(bmdma_active_if(bm));
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}
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} else if (error_status & BM_STATUS_RETRY_FLUSH) {
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ide_flush_cache(bmdma_active_if(bm));
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}
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}
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static void bmdma_restart_cb(void *opaque, int running, RunState state)
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{
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IDEDMA *dma = opaque;
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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if (!running)
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return;
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if (!bm->bh) {
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bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
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qemu_bh_schedule(bm->bh);
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}
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}
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static void bmdma_cancel(BMDMAState *bm)
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{
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if (bm->status & BM_STATUS_DMAING) {
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/* cancel DMA request */
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bmdma_set_inactive(&bm->dma);
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}
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}
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static int bmdma_reset(IDEDMA *dma)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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#ifdef DEBUG_IDE
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printf("ide: dma_reset\n");
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#endif
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bmdma_cancel(bm);
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bm->cmd = 0;
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bm->status = 0;
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bm->addr = 0;
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bm->cur_addr = 0;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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bm->sector_num = 0;
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bm->nsector = 0;
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return 0;
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}
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static int bmdma_start_transfer(IDEDMA *dma)
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{
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return 0;
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}
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static void bmdma_irq(void *opaque, int n, int level)
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{
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BMDMAState *bm = opaque;
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if (!level) {
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/* pass through lower */
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qemu_set_irq(bm->irq, level);
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return;
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}
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bm->status |= BM_STATUS_INT;
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/* trigger the real irq */
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qemu_set_irq(bm->irq, level);
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}
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
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{
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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/* Ignore writes to SSBM if it keeps the old value */
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if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
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if (!(val & BM_CMD_START)) {
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/*
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* We can't cancel Scatter Gather DMA in the middle of the
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* operation or a partial (not full) DMA transfer would reach
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* the storage so we wait for completion instead (we beahve
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* like if the DMA was completed by the time the guest trying
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* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
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* set).
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*
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* In the future we'll be able to safely cancel the I/O if the
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* whole DMA operation will be submitted to disk with a single
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* aio operation with preadv/pwritev.
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*/
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if (bm->bus->dma->aiocb) {
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qemu_aio_flush();
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assert(bm->bus->dma->aiocb == NULL);
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assert((bm->status & BM_STATUS_DMAING) == 0);
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}
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} else {
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bm->cur_addr = bm->addr;
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING;
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bmdma_active_if(bm), 0);
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}
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}
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}
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bm->cmd = val & 0x09;
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}
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static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
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unsigned width)
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{
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BMDMAState *bm = opaque;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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uint64_t data;
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data = (bm->addr >> (addr * 8)) & mask;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)*data);
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#endif
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return data;
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}
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static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
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uint64_t data, unsigned width)
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{
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BMDMAState *bm = opaque;
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int shift = addr * 8;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data);
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#endif
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bm->addr &= ~(mask << shift);
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bm->addr |= ((data & mask) << shift) & ~3;
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}
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MemoryRegionOps bmdma_addr_ioport_ops = {
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.read = bmdma_addr_read,
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.write = bmdma_addr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static bool ide_bmdma_current_needed(void *opaque)
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{
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BMDMAState *bm = opaque;
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return (bm->cur_prd_len != 0);
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}
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static bool ide_bmdma_status_needed(void *opaque)
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{
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BMDMAState *bm = opaque;
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/* Older versions abused some bits in the status register for internal
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* error state. If any of these bits are set, we must add a subsection to
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* transfer the real status register */
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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return ((bm->status & abused_bits) != 0);
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}
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static void ide_bmdma_pre_save(void *opaque)
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{
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BMDMAState *bm = opaque;
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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bm->migration_compat_status =
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(bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
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}
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/* This function accesses bm->bus->error_status which is loaded only after
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* BMDMA itself. This is why the function is called from ide_pci_post_load
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* instead of being registered with VMState where it would run too early. */
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static int ide_bmdma_post_load(void *opaque, int version_id)
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{
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BMDMAState *bm = opaque;
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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if (bm->status == 0) {
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bm->status = bm->migration_compat_status & ~abused_bits;
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bm->bus->error_status |= bm->migration_compat_status & abused_bits;
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}
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return 0;
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}
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static const VMStateDescription vmstate_bmdma_current = {
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.name = "ide bmdma_current",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(cur_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_last, BMDMAState),
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VMSTATE_UINT32(cur_prd_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_len, BMDMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_bmdma_status = {
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.name ="ide bmdma/status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(status, BMDMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_bmdma = {
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.name = "ide bmdma",
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.version_id = 3,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.pre_save = ide_bmdma_pre_save,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(cmd, BMDMAState),
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VMSTATE_UINT8(migration_compat_status, BMDMAState),
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VMSTATE_UINT32(addr, BMDMAState),
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VMSTATE_INT64(sector_num, BMDMAState),
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VMSTATE_UINT32(nsector, BMDMAState),
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VMSTATE_UINT8(unit, BMDMAState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (VMStateSubsection []) {
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{
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.vmsd = &vmstate_bmdma_current,
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.needed = ide_bmdma_current_needed,
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}, {
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.vmsd = &vmstate_bmdma_status,
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.needed = ide_bmdma_status_needed,
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}, {
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/* empty */
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}
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}
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};
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static int ide_pci_post_load(void *opaque, int version_id)
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{
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PCIIDEState *d = opaque;
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int i;
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for(i = 0; i < 2; i++) {
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/* current versions always store 0/1, but older version
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stored bigger values. We only need last bit */
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d->bmdma[i].unit &= 1;
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ide_bmdma_post_load(&d->bmdma[i], -1);
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}
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return 0;
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}
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const VMStateDescription vmstate_ide_pci = {
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.name = "ide",
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.version_id = 3,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = ide_pci_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PCIIDEState),
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VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
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vmstate_bmdma, BMDMAState),
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VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
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VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
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VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
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VMSTATE_END_OF_LIST()
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}
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};
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void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
|
|
{
|
|
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
|
|
static const int bus[4] = { 0, 0, 1, 1 };
|
|
static const int unit[4] = { 0, 1, 0, 1 };
|
|
int i;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (hd_table[i] == NULL)
|
|
continue;
|
|
ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
|
|
}
|
|
}
|
|
|
|
static const struct IDEDMAOps bmdma_ops = {
|
|
.start_dma = bmdma_start_dma,
|
|
.start_transfer = bmdma_start_transfer,
|
|
.prepare_buf = bmdma_prepare_buf,
|
|
.rw_buf = bmdma_rw_buf,
|
|
.set_unit = bmdma_set_unit,
|
|
.add_status = bmdma_add_status,
|
|
.set_inactive = bmdma_set_inactive,
|
|
.restart_cb = bmdma_restart_cb,
|
|
.reset = bmdma_reset,
|
|
};
|
|
|
|
void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
|
|
{
|
|
qemu_irq *irq;
|
|
|
|
if (bus->dma == &bm->dma) {
|
|
return;
|
|
}
|
|
|
|
bm->dma.ops = &bmdma_ops;
|
|
bus->dma = &bm->dma;
|
|
bm->irq = bus->irq;
|
|
irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
|
|
bus->irq = *irq;
|
|
bm->pci_dev = d;
|
|
}
|