Implement the MVE VNEG insn (both integer and floating point forms). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-9-peter.maydell@linaro.org
270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/*
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* ARM translation: M-profile MVE instructions
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "tcg/tcg-op-gvec.h"
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#include "exec/exec-all.h"
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#include "exec/gen-icount.h"
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#include "translate.h"
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#include "translate-a32.h"
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/* Include the generated decoder */
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#include "decode-mve.c.inc"
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typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
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/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
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static inline long mve_qreg_offset(unsigned reg)
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{
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return offsetof(CPUARMState, vfp.zregs[reg].d[0]);
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}
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static TCGv_ptr mve_qreg_ptr(unsigned reg)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
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return ret;
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}
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static bool mve_check_qreg_bank(DisasContext *s, int qmask)
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{
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/*
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* Check whether Qregs are in range. For v8.1M only Q0..Q7
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* are supported, see VFPSmallRegisterBank().
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*/
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return qmask < 8;
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}
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static bool mve_eci_check(DisasContext *s)
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{
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/*
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* This is a beatwise insn: check that ECI is valid (not a
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* reserved value) and note that we are handling it.
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* Return true if OK, false if we generated an exception.
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*/
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s->eci_handled = true;
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switch (s->eci) {
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case ECI_NONE:
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case ECI_A0:
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case ECI_A0A1:
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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return true;
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default:
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/* Reserved value: INVSTATE UsageFault */
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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return false;
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}
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}
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static void mve_update_eci(DisasContext *s)
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{
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/*
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* The helper function will always update the CPUState field,
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* so we only need to update the DisasContext field.
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*/
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if (s->eci) {
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s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE;
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}
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}
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static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
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{
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TCGv_i32 addr;
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uint32_t offset;
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TCGv_ptr qreg;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd) ||
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!fn) {
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return false;
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}
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/* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
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if (a->rn == 15 || (a->rn == 13 && a->w)) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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offset = a->imm << a->size;
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if (!a->a) {
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offset = -offset;
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}
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addr = load_reg(s, a->rn);
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if (a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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qreg = mve_qreg_ptr(a->qd);
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fn(cpu_env, qreg, addr);
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tcg_temp_free_ptr(qreg);
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/*
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* Writeback always happens after the last beat of the insn,
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* regardless of predication
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*/
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if (a->w) {
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if (!a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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store_reg(s, a->rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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mve_update_eci(s);
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return true;
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}
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static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
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{
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static MVEGenLdStFn * const ldstfns[4][2] = {
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{ gen_helper_mve_vstrb, gen_helper_mve_vldrb },
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{ gen_helper_mve_vstrh, gen_helper_mve_vldrh },
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{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
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{ NULL, NULL }
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};
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return do_ldst(s, a, ldstfns[a->size][a->l]);
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}
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#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
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static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
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{ \
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static MVEGenLdStFn * const ldstfns[2][2] = { \
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{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
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{ NULL, gen_helper_mve_##ULD }, \
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}; \
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return do_ldst(s, a, ldstfns[a->u][a->l]); \
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}
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DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
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DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
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DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
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static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
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{
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TCGv_ptr qd, qm;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd | a->qm) ||
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!fn) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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qd = mve_qreg_ptr(a->qd);
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qm = mve_qreg_ptr(a->qm);
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fn(cpu_env, qd, qm);
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tcg_temp_free_ptr(qd);
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tcg_temp_free_ptr(qm);
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mve_update_eci(s);
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return true;
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}
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#define DO_1OP(INSN, FN) \
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static bool trans_##INSN(DisasContext *s, arg_1op *a) \
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{ \
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static MVEGenOneOpFn * const fns[] = { \
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gen_helper_mve_##FN##b, \
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gen_helper_mve_##FN##h, \
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gen_helper_mve_##FN##w, \
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NULL, \
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}; \
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return do_1op(s, a, fns[a->size]); \
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}
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DO_1OP(VCLZ, vclz)
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DO_1OP(VCLS, vcls)
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DO_1OP(VABS, vabs)
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DO_1OP(VNEG, vneg)
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static bool trans_VREV16(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev16b,
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NULL,
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NULL,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VREV32(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev32b,
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gen_helper_mve_vrev32h,
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NULL,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VREV64(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev64b,
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gen_helper_mve_vrev64h,
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gen_helper_mve_vrev64w,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VMVN(DisasContext *s, arg_1op *a)
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{
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return do_1op(s, a, gen_helper_mve_vmvn);
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}
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static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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NULL,
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gen_helper_mve_vfabsh,
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gen_helper_mve_vfabss,
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NULL,
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};
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if (!dc_isar_feature(aa32_mve_fp, s)) {
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return false;
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}
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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NULL,
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gen_helper_mve_vfnegh,
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gen_helper_mve_vfnegs,
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NULL,
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};
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if (!dc_isar_feature(aa32_mve_fp, s)) {
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return false;
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}
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return do_1op(s, a, fns[a->size]);
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}
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