This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
244 lines
5.6 KiB
C
244 lines
5.6 KiB
C
/*
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* QEMU model of the Milkymist UART block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/uart.pdf
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-char.h"
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#include "qemu-error.h"
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enum {
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R_RXTX = 0,
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R_DIV,
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R_STAT,
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R_CTRL,
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R_DBG,
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R_MAX
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};
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enum {
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STAT_THRE = (1<<0),
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STAT_RX_EVT = (1<<1),
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STAT_TX_EVT = (1<<2),
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};
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enum {
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CTRL_RX_IRQ_EN = (1<<0),
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CTRL_TX_IRQ_EN = (1<<1),
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CTRL_THRU_EN = (1<<2),
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};
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enum {
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DBG_BREAK_EN = (1<<0),
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};
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struct MilkymistUartState {
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SysBusDevice busdev;
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MemoryRegion regs_region;
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t regs[R_MAX];
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};
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typedef struct MilkymistUartState MilkymistUartState;
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static void uart_update_irq(MilkymistUartState *s)
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{
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int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
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int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
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int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
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int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
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if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
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trace_milkymist_uart_raise_irq();
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qemu_irq_raise(s->irq);
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} else {
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trace_milkymist_uart_lower_irq();
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qemu_irq_lower(s->irq);
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}
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}
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static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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MilkymistUartState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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r = s->regs[addr];
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break;
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case R_DIV:
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case R_STAT:
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case R_CTRL:
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case R_DBG:
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_uart: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_uart_memory_read(addr << 2, r);
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return r;
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}
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static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
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unsigned size)
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{
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MilkymistUartState *s = opaque;
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unsigned char ch = value;
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trace_milkymist_uart_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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}
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s->regs[R_STAT] |= STAT_TX_EVT;
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break;
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case R_DIV:
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case R_CTRL:
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case R_DBG:
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s->regs[addr] = value;
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break;
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case R_STAT:
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/* write one to clear bits */
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s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
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break;
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default:
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error_report("milkymist_uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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uart_update_irq(s);
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}
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static const MemoryRegionOps uart_mmio_ops = {
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.read = uart_read,
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.write = uart_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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MilkymistUartState *s = opaque;
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assert(!(s->regs[R_STAT] & STAT_RX_EVT));
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s->regs[R_STAT] |= STAT_RX_EVT;
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s->regs[R_RXTX] = *buf;
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uart_update_irq(s);
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}
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static int uart_can_rx(void *opaque)
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{
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MilkymistUartState *s = opaque;
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return !(s->regs[R_STAT] & STAT_RX_EVT);
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static void milkymist_uart_reset(DeviceState *d)
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{
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MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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/* THRE is always set */
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s->regs[R_STAT] = STAT_THRE;
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}
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static int milkymist_uart_init(SysBusDevice *dev)
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{
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MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
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"milkymist-uart", R_MAX * 4);
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sysbus_init_mmio(dev, &s->regs_region);
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s->chr = qdev_init_chardev(&dev->qdev);
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_milkymist_uart = {
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.name = "milkymist-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static void milkymist_uart_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = milkymist_uart_init;
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dc->reset = milkymist_uart_reset;
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dc->vmsd = &vmstate_milkymist_uart;
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}
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static TypeInfo milkymist_uart_info = {
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.name = "milkymist-uart",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MilkymistUartState),
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.class_init = milkymist_uart_class_init,
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};
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static void milkymist_uart_register(void)
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{
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type_register_static(&milkymist_uart_info);
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}
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device_init(milkymist_uart_register)
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