Add support for SD. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
564 lines
20 KiB
C
564 lines
20 KiB
C
/*
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* Xilinx Versal Virtual board.
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*
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* Copyright (c) 2018 Xilinx Inc.
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* Written by Edgar E. Iglesias
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/arm/sysbus-fdt.h"
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#include "hw/arm/fdt.h"
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#include "cpu.h"
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#include "hw/qdev-properties.h"
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#include "hw/arm/xlnx-versal.h"
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#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
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#define XLNX_VERSAL_VIRT_MACHINE(obj) \
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OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
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typedef struct VersalVirt {
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MachineState parent_obj;
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Versal soc;
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void *fdt;
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int fdt_size;
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struct {
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uint32_t gic;
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uint32_t ethernet_phy[2];
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uint32_t clk_125Mhz;
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uint32_t clk_25Mhz;
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} phandle;
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struct arm_boot_info binfo;
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struct {
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bool secure;
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} cfg;
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} VersalVirt;
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static void fdt_create(VersalVirt *s)
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{
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MachineClass *mc = MACHINE_GET_CLASS(s);
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int i;
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s->fdt = create_device_tree(&s->fdt_size);
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if (!s->fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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/* Allocate all phandles. */
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s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
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for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
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s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
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}
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s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
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s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
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/* Create /chosen node for load_dtb. */
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qemu_fdt_add_subnode(s->fdt, "/chosen");
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/* Header */
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qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
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qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
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qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
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}
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static void fdt_add_clk_node(VersalVirt *s, const char *name,
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unsigned int freq_hz, uint32_t phandle)
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{
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
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qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
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qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
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qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
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qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
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}
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static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
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{
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int i;
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qemu_fdt_add_subnode(s->fdt, "/cpus");
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qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
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for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
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char *name = g_strdup_printf("/cpus/cpu@%d", i);
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ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
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if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
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qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
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}
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qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
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qemu_fdt_setprop_string(s->fdt, name, "compatible",
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armcpu->dtb_compatible);
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g_free(name);
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}
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}
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static void fdt_add_gic_nodes(VersalVirt *s)
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{
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char *nodename;
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nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
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qemu_fdt_add_subnode(s->fdt, nodename);
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qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
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qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
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2, MM_GIC_APU_DIST_MAIN,
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2, MM_GIC_APU_DIST_MAIN_SIZE,
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2, MM_GIC_APU_REDIST_0,
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2, MM_GIC_APU_REDIST_0_SIZE);
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qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
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qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
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g_free(nodename);
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}
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static void fdt_add_timer_nodes(VersalVirt *s)
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{
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const char compat[] = "arm,armv8-timer";
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uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
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qemu_fdt_add_subnode(s->fdt, "/timer");
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qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
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qemu_fdt_setprop(s->fdt, "/timer", "compatible",
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compat, sizeof(compat));
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}
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static void fdt_add_uart_nodes(VersalVirt *s)
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{
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uint64_t addrs[] = { MM_UART1, MM_UART0 };
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unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
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const char compat[] = "arm,pl011\0arm,sbsa-uart";
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const char clocknames[] = "uartclk\0apb_pclk";
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int i;
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for (i = 0; i < ARRAY_SIZE(addrs); i++) {
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char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addrs[i], 2, 0x1000);
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qemu_fdt_setprop(s->fdt, name, "compatible",
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compat, sizeof(compat));
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qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
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if (addrs[i] == MM_UART0) {
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/* Select UART0. */
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qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
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}
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g_free(name);
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}
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}
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static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
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uint32_t phandle)
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{
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char *name = g_strdup_printf("%s/fixed-link", gemname);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
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qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
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qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
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g_free(name);
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}
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static void fdt_add_gem_nodes(VersalVirt *s)
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{
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uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
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unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
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const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
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const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
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int i;
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for (i = 0; i < ARRAY_SIZE(addrs); i++) {
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char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
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qemu_fdt_add_subnode(s->fdt, name);
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fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
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qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
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qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
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s->phandle.ethernet_phy[i]);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI,
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addrs[i], 2, 0x1000);
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qemu_fdt_setprop(s->fdt, name, "compatible",
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compat_gem, sizeof(compat_gem));
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qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
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qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
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g_free(name);
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}
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}
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static void fdt_add_zdma_nodes(VersalVirt *s)
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{
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const char clocknames[] = "clk_main\0clk_apb";
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const char compat[] = "xlnx,zynqmp-dma-1.0";
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int i;
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for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
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uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
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char *name = g_strdup_printf("/dma@%" PRIx64, addr);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addr, 2, 0x1000);
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qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
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g_free(name);
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}
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}
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static void fdt_add_sd_nodes(VersalVirt *s)
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{
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const char clocknames[] = "clk_xin\0clk_ahb";
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const char compat[] = "arasan,sdhci-8.9a";
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int i;
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for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
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uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
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char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addr, 2, MM_PMC_SD0_SIZE);
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qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
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g_free(name);
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}
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}
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static void fdt_nop_memory_nodes(void *fdt, Error **errp)
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{
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Error *err = NULL;
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char **node_path;
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int n = 0;
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node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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while (node_path[n]) {
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if (g_str_has_prefix(node_path[n], "/memory")) {
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qemu_fdt_nop_node(fdt, node_path[n]);
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}
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n++;
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}
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g_strfreev(node_path);
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}
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static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
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{
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/* Describes the various split DDR access regions. */
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static const struct {
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uint64_t base;
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uint64_t size;
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} addr_ranges[] = {
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{ MM_TOP_DDR, MM_TOP_DDR_SIZE },
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{ MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
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{ MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
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{ MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
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};
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uint64_t mem_reg_prop[8] = {0};
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uint64_t size = ram_size;
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Error *err = NULL;
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char *name;
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int i;
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fdt_nop_memory_nodes(fdt, &err);
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if (err) {
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error_report_err(err);
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return;
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}
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name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
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for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
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uint64_t mapsize;
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mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
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mem_reg_prop[i * 2] = addr_ranges[i].base;
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mem_reg_prop[i * 2 + 1] = mapsize;
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size -= mapsize;
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}
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qemu_fdt_add_subnode(fdt, name);
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qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
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switch (i) {
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case 1:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1]);
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break;
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case 2:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3]);
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break;
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case 3:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3],
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2, mem_reg_prop[4],
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2, mem_reg_prop[5]);
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break;
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case 4:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3],
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2, mem_reg_prop[4],
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2, mem_reg_prop[5],
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2, mem_reg_prop[6],
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2, mem_reg_prop[7]);
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break;
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default:
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g_assert_not_reached();
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}
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g_free(name);
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}
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static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
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void *fdt)
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{
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VersalVirt *s = container_of(binfo, VersalVirt, binfo);
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fdt_add_memory_nodes(s, fdt, binfo->ram_size);
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}
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static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
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int *fdt_size)
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{
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const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
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*fdt_size = board->fdt_size;
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return board->fdt;
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}
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#define NUM_VIRTIO_TRANSPORT 8
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static void create_virtio_regions(VersalVirt *s)
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{
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|
int virtio_mmio_size = 0x200;
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
|
|
char *name = g_strdup_printf("virtio%d", i);
|
|
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
|
|
int irq = VERSAL_RSVD_IRQ_FIRST + i;
|
|
MemoryRegion *mr;
|
|
DeviceState *dev;
|
|
qemu_irq pic_irq;
|
|
|
|
pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
|
|
dev = qdev_create(NULL, "virtio-mmio");
|
|
object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
|
|
&error_fatal);
|
|
qdev_init_nofail(dev);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
|
|
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
|
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
|
|
g_free(name);
|
|
}
|
|
|
|
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
|
|
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
|
|
int irq = VERSAL_RSVD_IRQ_FIRST + i;
|
|
char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
|
|
|
|
qemu_fdt_add_subnode(s->fdt, name);
|
|
qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
|
|
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
|
|
GIC_FDT_IRQ_TYPE_SPI, irq,
|
|
GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
|
|
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
|
|
2, base, 2, virtio_mmio_size);
|
|
qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
|
|
g_free(name);
|
|
}
|
|
}
|
|
|
|
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
|
|
{
|
|
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
|
|
DeviceState *card;
|
|
|
|
card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
|
|
object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
|
|
&error_fatal);
|
|
qdev_prop_set_drive(card, "drive", blk, &error_fatal);
|
|
object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
|
|
}
|
|
|
|
static void versal_virt_init(MachineState *machine)
|
|
{
|
|
VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
|
|
int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
|
|
int i;
|
|
|
|
/*
|
|
* If the user provides an Operating System to be loaded, we expect them
|
|
* to use the -kernel command line option.
|
|
*
|
|
* Users can load firmware or boot-loaders with the -device loader options.
|
|
*
|
|
* When loading an OS, we generate a dtb and let arm_load_kernel() select
|
|
* where it gets loaded. This dtb will be passed to the kernel in x0.
|
|
*
|
|
* If there's no -kernel option, we generate a DTB and place it at 0x1000
|
|
* for the bootloaders or firmware to pick up.
|
|
*
|
|
* If users want to provide their own DTB, they can use the -dtb option.
|
|
* These dtb's will have their memory nodes modified to match QEMU's
|
|
* selected ram_size option before they get passed to the kernel or fw.
|
|
*
|
|
* When loading an OS, we turn on QEMU's PSCI implementation with SMC
|
|
* as the PSCI conduit. When there's no -kernel, we assume the user
|
|
* provides EL3 firmware to handle PSCI.
|
|
*/
|
|
if (machine->kernel_filename) {
|
|
psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
|
}
|
|
|
|
sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
|
|
sizeof(s->soc), TYPE_XLNX_VERSAL);
|
|
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
|
|
"ddr", &error_abort);
|
|
object_property_set_int(OBJECT(&s->soc), psci_conduit,
|
|
"psci-conduit", &error_abort);
|
|
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
|
|
|
|
fdt_create(s);
|
|
create_virtio_regions(s);
|
|
fdt_add_gem_nodes(s);
|
|
fdt_add_uart_nodes(s);
|
|
fdt_add_gic_nodes(s);
|
|
fdt_add_timer_nodes(s);
|
|
fdt_add_zdma_nodes(s);
|
|
fdt_add_sd_nodes(s);
|
|
fdt_add_cpu_nodes(s, psci_conduit);
|
|
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
|
|
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
|
|
|
|
/* Make the APU cpu address space visible to virtio and other
|
|
* modules unaware of muliple address-spaces. */
|
|
memory_region_add_subregion_overlap(get_system_memory(),
|
|
0, &s->soc.fpd.apu.mr, 0);
|
|
|
|
/* Plugin SD cards. */
|
|
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
|
|
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
|
|
}
|
|
|
|
s->binfo.ram_size = machine->ram_size;
|
|
s->binfo.loader_start = 0x0;
|
|
s->binfo.get_dtb = versal_virt_get_dtb;
|
|
s->binfo.modify_dtb = versal_virt_modify_dtb;
|
|
if (machine->kernel_filename) {
|
|
arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
|
|
} else {
|
|
AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
|
|
&s->binfo);
|
|
/* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
|
|
* Offset things by 4K. */
|
|
s->binfo.loader_start = 0x1000;
|
|
s->binfo.dtb_limit = 0x1000000;
|
|
if (arm_load_dtb(s->binfo.loader_start,
|
|
&s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
|
|
exit(EXIT_FAILURE);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void versal_virt_machine_instance_init(Object *obj)
|
|
{
|
|
}
|
|
|
|
static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Xilinx Versal Virtual development board";
|
|
mc->init = versal_virt_init;
|
|
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
|
|
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
|
|
mc->no_cdrom = true;
|
|
mc->default_ram_id = "ddr";
|
|
}
|
|
|
|
static const TypeInfo versal_virt_machine_init_typeinfo = {
|
|
.name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = versal_virt_machine_class_init,
|
|
.instance_init = versal_virt_machine_instance_init,
|
|
.instance_size = sizeof(VersalVirt),
|
|
};
|
|
|
|
static void versal_virt_machine_init_register_types(void)
|
|
{
|
|
type_register_static(&versal_virt_machine_init_typeinfo);
|
|
}
|
|
|
|
type_init(versal_virt_machine_init_register_types)
|
|
|