The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
247 lines
7.9 KiB
C
247 lines
7.9 KiB
C
/*
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* Nordic Semiconductor nRF51 SoC
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* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
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*
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* Copyright 2018 Joel Stanley <joel@jms.id.au>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/arm/boot.h"
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#include "hw/sysbus.h"
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#include "hw/misc/unimp.h"
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#include "exec/address-spaces.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/arm/nrf51.h"
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#include "hw/arm/nrf51_soc.h"
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/*
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* The size and base is for the NRF51822 part. If other parts
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* are supported in the future, add a sub-class of NRF51SoC for
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* the specific variants
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*/
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#define NRF51822_FLASH_PAGES 256
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#define NRF51822_SRAM_PAGES 16
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#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
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#define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
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#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
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static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
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__func__, addr, size);
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return 1;
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}
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static void clock_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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__func__, addr, data, size);
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}
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static const MemoryRegionOps clock_ops = {
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.read = clock_read,
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.write = clock_write
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};
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static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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NRF51State *s = NRF51_SOC(dev_soc);
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MemoryRegion *mr;
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Error *err = NULL;
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uint8_t i = 0;
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hwaddr base_addr = 0;
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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return;
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}
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object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
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memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
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/* UART */
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object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
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memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu),
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BASE_TO_IRQ(NRF51_UART_BASE)));
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/* RNG */
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object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
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memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu),
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BASE_TO_IRQ(NRF51_RNG_BASE)));
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/* UICR, FICR, NVMC, FLASH */
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object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
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memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
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memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
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memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
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memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
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/* GPIO */
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object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
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memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
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/* Pass all GPIOs to the SOC layer so they are available to the board */
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qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
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/* TIMER */
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for (i = 0; i < NRF51_NUM_TIMERS; i++) {
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object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu),
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BASE_TO_IRQ(base_addr)));
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}
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/* STUB Peripherals */
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memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
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"nrf51_soc.clock", NRF51_PERIPHERAL_SIZE);
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memory_region_add_subregion_overlap(&s->container,
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NRF51_IOMEM_BASE, &s->clock, -1);
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create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
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NRF51_IOMEM_SIZE);
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create_unimplemented_device("nrf51_soc.private",
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NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
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}
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static void nrf51_soc_init(Object *obj)
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{
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uint8_t i = 0;
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NRF51State *s = NRF51_SOC(obj);
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memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
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sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
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TYPE_ARMV7M);
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qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
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ARM_CPU_TYPE_NAME("cortex-m0"));
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qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
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sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
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TYPE_NRF51_UART);
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object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
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sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
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TYPE_NRF51_RNG);
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sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
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sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
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TYPE_NRF51_GPIO);
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for (i = 0; i < NRF51_NUM_TIMERS; i++) {
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sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
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sizeof(s->timer[i]), TYPE_NRF51_TIMER);
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}
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}
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static Property nrf51_soc_properties[] = {
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DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
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DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
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NRF51822_FLASH_SIZE),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nrf51_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = nrf51_soc_realize;
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device_class_set_props(dc, nrf51_soc_properties);
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}
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static const TypeInfo nrf51_soc_info = {
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.name = TYPE_NRF51_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NRF51State),
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.instance_init = nrf51_soc_init,
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.class_init = nrf51_soc_class_init,
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};
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static void nrf51_soc_types(void)
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{
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type_register_static(&nrf51_soc_info);
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}
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type_init(nrf51_soc_types)
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