PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: Alexander Graf <agraf@suse.de>
421 lines
12 KiB
C
421 lines
12 KiB
C
/*
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* QEMU PowerPC E500 embedded processors pci controller emulation
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc4xx_pci.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "hw.h"
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#include "hw/ppc/e500-ccsr.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "bswap.h"
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#ifdef DEBUG_PCI
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#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
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#else
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#define pci_debug(fmt, ...)
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#endif
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#define PCIE500_CFGADDR 0x0
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#define PCIE500_CFGDATA 0x4
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#define PCIE500_REG_BASE 0xC00
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#define PCIE500_ALL_SIZE 0x1000
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#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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#define PCIE500_PCI_IOLEN 0x10000ULL
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#define PPCE500_PCI_CONFIG_ADDR 0x0
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#define PPCE500_PCI_CONFIG_DATA 0x4
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#define PPCE500_PCI_INTACK 0x8
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#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
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#define PCI_POTAR 0x0
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#define PCI_POTEAR 0x4
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#define PCI_POWBAR 0x8
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#define PCI_POWAR 0x10
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#define PCI_PITAR 0x0
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#define PCI_PIWBAR 0x8
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#define PCI_PIWBEAR 0xC
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#define PCI_PIWAR 0x10
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#define PPCE500_PCI_NR_POBS 5
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#define PPCE500_PCI_NR_PIBS 3
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struct pci_outbound {
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uint32_t potar;
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uint32_t potear;
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uint32_t powbar;
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uint32_t powar;
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};
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struct pci_inbound {
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uint32_t pitar;
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uint32_t piwbar;
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uint32_t piwbear;
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uint32_t piwar;
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};
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#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
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#define PPC_E500_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
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struct PPCE500PCIState {
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PCIHostState parent_obj;
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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uint32_t gasket_time;
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qemu_irq irq[4];
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/* mmio maps */
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MemoryRegion container;
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MemoryRegion iomem;
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MemoryRegion pio;
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};
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#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
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#define PPC_E500_PCI_BRIDGE(obj) \
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OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
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struct PPCE500PCIBridgeState {
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/*< private >*/
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PCIDevice parent;
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/*< public >*/
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MemoryRegion bar0;
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};
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typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
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typedef struct PPCE500PCIState PPCE500PCIState;
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static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
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unsigned size)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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uint32_t value = 0;
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int idx;
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win = addr & 0xfe0;
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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idx = (addr >> 5) & 0x7;
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switch (addr & 0xC) {
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case PCI_POTAR:
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value = pci->pob[idx].potar;
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break;
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case PCI_POTEAR:
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value = pci->pob[idx].potear;
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break;
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case PCI_POWBAR:
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value = pci->pob[idx].powbar;
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break;
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case PCI_POWAR:
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value = pci->pob[idx].powar;
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break;
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default:
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break;
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}
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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idx = ((addr >> 5) & 0x3) - 1;
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switch (addr & 0xC) {
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case PCI_PITAR:
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value = pci->pib[idx].pitar;
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break;
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case PCI_PIWBAR:
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value = pci->pib[idx].piwbar;
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break;
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case PCI_PIWBEAR:
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value = pci->pib[idx].piwbear;
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break;
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case PCI_PIWAR:
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value = pci->pib[idx].piwar;
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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value = pci->gasket_time;
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break;
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default:
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break;
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}
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pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
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win, addr, value);
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return value;
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}
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static void pci_reg_write4(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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int idx;
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win = addr & 0xfe0;
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pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
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__func__, (unsigned)value, win, addr);
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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idx = (addr >> 5) & 0x7;
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switch (addr & 0xC) {
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case PCI_POTAR:
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pci->pob[idx].potar = value;
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break;
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case PCI_POTEAR:
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pci->pob[idx].potear = value;
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break;
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case PCI_POWBAR:
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pci->pob[idx].powbar = value;
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break;
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case PCI_POWAR:
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pci->pob[idx].powar = value;
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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idx = ((addr >> 5) & 0x3) - 1;
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switch (addr & 0xC) {
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case PCI_PITAR:
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pci->pib[idx].pitar = value;
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break;
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case PCI_PIWBAR:
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pci->pib[idx].piwbar = value;
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break;
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case PCI_PIWBEAR:
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pci->pib[idx].piwbear = value;
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break;
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case PCI_PIWAR:
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pci->pib[idx].piwar = value;
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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pci->gasket_time = value;
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break;
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default:
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break;
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};
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}
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static const MemoryRegionOps e500_pci_reg_ops = {
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.read = pci_reg_read4,
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.write = pci_reg_write4,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int devno = pci_dev->devfn >> 3, ret = 0;
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switch (devno) {
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/* Two PCI slot */
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case 0x11:
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case 0x12:
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ret = (irq_num + devno - 0x10) % 4;
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break;
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default:
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printf("Error:%s:unknown dev number\n", __func__);
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}
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pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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pci_dev->devfn, irq_num, ret, devno);
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return ret;
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}
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static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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qemu_set_irq(pic[irq_num], level);
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}
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static const VMStateDescription vmstate_pci_outbound = {
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.name = "pci_outbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(potar, struct pci_outbound),
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VMSTATE_UINT32(potear, struct pci_outbound),
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VMSTATE_UINT32(powbar, struct pci_outbound),
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VMSTATE_UINT32(powar, struct pci_outbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_inbound = {
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.name = "pci_inbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(pitar, struct pci_inbound),
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VMSTATE_UINT32(piwbar, struct pci_inbound),
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VMSTATE_UINT32(piwbear, struct pci_inbound),
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VMSTATE_UINT32(piwar, struct pci_inbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_ppce500_pci = {
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.name = "ppce500_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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vmstate_pci_outbound, struct pci_outbound),
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VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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vmstate_pci_outbound, struct pci_inbound),
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VMSTATE_UINT32(gasket_time, PPCE500PCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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#include "exec-memory.h"
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static int e500_pcihost_bridge_initfn(PCIDevice *d)
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{
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PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
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PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
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"/e500-ccsr"));
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memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space,
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0, int128_get64(ccsr->ccsr_space.size));
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pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
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return 0;
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}
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static int e500_pcihost_initfn(SysBusDevice *dev)
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{
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PCIHostState *h;
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PPCE500PCIState *s;
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PCIBus *b;
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int i;
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MemoryRegion *address_space_mem = get_system_memory();
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h = PCI_HOST_BRIDGE(dev);
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s = PPC_E500_PCI_HOST_BRIDGE(dev);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
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b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq, s->irq, address_space_mem,
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&s->pio, PCI_DEVFN(0x11, 0), 4);
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h->bus = b;
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pci_create_simple(b, 0, "e500-host-bridge");
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memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
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memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
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"pci-conf-idx", 4);
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memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
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"pci-conf-data", 4);
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memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
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"pci.reg", PCIE500_REG_SIZE);
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memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
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memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
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memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
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sysbus_init_mmio(dev, &s->container);
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sysbus_init_mmio(dev, &s->pio);
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return 0;
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}
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static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = e500_pcihost_bridge_initfn;
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k->vendor_id = PCI_VENDOR_ID_FREESCALE;
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k->device_id = PCI_DEVICE_ID_MPC8533E;
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k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
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dc->desc = "Host bridge";
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}
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static const TypeInfo e500_host_bridge_info = {
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.name = "e500-host-bridge",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PPCE500PCIBridgeState),
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.class_init = e500_host_bridge_class_init,
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};
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static void e500_pcihost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = e500_pcihost_initfn;
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dc->vmsd = &vmstate_ppce500_pci;
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}
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static const TypeInfo e500_pcihost_info = {
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.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(PPCE500PCIState),
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.class_init = e500_pcihost_class_init,
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};
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static void e500_pci_register_types(void)
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{
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type_register_static(&e500_pcihost_info);
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type_register_static(&e500_host_bridge_info);
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}
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type_init(e500_pci_register_types)
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