On Xen MSIs can be remapped into pirqs, which are a type of event channels. It's mostly for the benefit of PCI passthrough devices, to avoid the overhead of interacting with the emulated lapic. However remapping interrupts and MSIs is also supported for emulated devices, such as the e1000 and virtio-net. When an interrupt or an MSI is remapped into a pirq, masking and unmasking is done by masking and unmasking the event channel. The masking bit on the PCI config space or MSI-X table should be ignored, but it isn't at the moment. As a consequence emulated devices which use MSI or MSI-X, such as virtio-net, don't work properly (the guest doesn't receive any notifications). The mechanism was working properly when xen_apic was introduced, but I haven't narrowed down which commit in particular is causing the regression. Fix the issue by ignoring the masking bit for MSI and MSI-X which have been remapped into pirqs. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
409 lines
12 KiB
C
409 lines
12 KiB
C
/*
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* msi.c
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/msi.h"
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#include "hw/xen/xen.h"
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#include "qemu/range.h"
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/* PCI_MSI_ADDRESS_LO */
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#define PCI_MSI_ADDRESS_LO_MASK (~0x3)
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/* If we get rid of cap allocator, we won't need those. */
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#define PCI_MSI_32_SIZEOF 0x0a
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#define PCI_MSI_64_SIZEOF 0x0e
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#define PCI_MSI_32M_SIZEOF 0x14
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#define PCI_MSI_64M_SIZEOF 0x18
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#define PCI_MSI_VECTORS_MAX 32
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/* Flag for interrupt controller to declare MSI/MSI-X support */
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bool msi_supported;
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/* If we get rid of cap allocator, we won't need this. */
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static inline uint8_t msi_cap_sizeof(uint16_t flags)
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{
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switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
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case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
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return PCI_MSI_64M_SIZEOF;
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case PCI_MSI_FLAGS_64BIT:
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return PCI_MSI_64_SIZEOF;
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case PCI_MSI_FLAGS_MASKBIT:
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return PCI_MSI_32M_SIZEOF;
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case 0:
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return PCI_MSI_32_SIZEOF;
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default:
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abort();
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break;
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}
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return 0;
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}
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//#define MSI_DEBUG
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#ifdef MSI_DEBUG
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# define MSI_DPRINTF(fmt, ...) \
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fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
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#else
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# define MSI_DPRINTF(fmt, ...) do { } while (0)
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#endif
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#define MSI_DEV_PRINTF(dev, fmt, ...) \
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MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
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static inline unsigned int msi_nr_vectors(uint16_t flags)
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{
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return 1U <<
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((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
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}
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static inline uint8_t msi_flags_off(const PCIDevice* dev)
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{
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return dev->msi_cap + PCI_MSI_FLAGS;
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}
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static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
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{
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return dev->msi_cap + PCI_MSI_ADDRESS_LO;
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}
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static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
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{
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return dev->msi_cap + PCI_MSI_ADDRESS_HI;
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}
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static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
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{
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return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
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}
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static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
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{
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return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
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}
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static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
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{
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return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
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}
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/*
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* Special API for POWER to configure the vectors through
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* a side channel. Should never be used by devices.
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*/
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void msi_set_message(PCIDevice *dev, MSIMessage msg)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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if (msi64bit) {
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pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
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} else {
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pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
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}
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pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
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}
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MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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unsigned int nr_vectors = msi_nr_vectors(flags);
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MSIMessage msg;
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assert(vector < nr_vectors);
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if (msi64bit) {
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msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
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} else {
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msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
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}
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/* upper bit 31:16 is zero */
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msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
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if (nr_vectors > 1) {
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msg.data &= ~(nr_vectors - 1);
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msg.data |= vector;
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}
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return msg;
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}
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bool msi_enabled(const PCIDevice *dev)
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{
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return msi_present(dev) &&
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(pci_get_word(dev->config + msi_flags_off(dev)) &
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PCI_MSI_FLAGS_ENABLE);
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}
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int msi_init(struct PCIDevice *dev, uint8_t offset,
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unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
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{
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unsigned int vectors_order;
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uint16_t flags;
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uint8_t cap_size;
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int config_offset;
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if (!msi_supported) {
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return -ENOTSUP;
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}
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MSI_DEV_PRINTF(dev,
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"init offset: 0x%"PRIx8" vector: %"PRId8
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" 64bit %d mask %d\n",
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offset, nr_vectors, msi64bit, msi_per_vector_mask);
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assert(!(nr_vectors & (nr_vectors - 1))); /* power of 2 */
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assert(nr_vectors > 0);
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assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
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/* the nr of MSI vectors is up to 32 */
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vectors_order = ctz32(nr_vectors);
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flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
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if (msi64bit) {
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flags |= PCI_MSI_FLAGS_64BIT;
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}
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if (msi_per_vector_mask) {
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flags |= PCI_MSI_FLAGS_MASKBIT;
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}
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cap_size = msi_cap_sizeof(flags);
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config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
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if (config_offset < 0) {
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return config_offset;
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}
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dev->msi_cap = config_offset;
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dev->cap_present |= QEMU_PCI_CAP_MSI;
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pci_set_word(dev->config + msi_flags_off(dev), flags);
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pci_set_word(dev->wmask + msi_flags_off(dev),
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PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
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pci_set_long(dev->wmask + msi_address_lo_off(dev),
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PCI_MSI_ADDRESS_LO_MASK);
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if (msi64bit) {
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pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
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}
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pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
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if (msi_per_vector_mask) {
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/* Make mask bits 0 to nr_vectors - 1 writable. */
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pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
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0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
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}
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return config_offset;
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}
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void msi_uninit(struct PCIDevice *dev)
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{
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uint16_t flags;
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uint8_t cap_size;
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if (!msi_present(dev)) {
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return;
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}
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flags = pci_get_word(dev->config + msi_flags_off(dev));
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cap_size = msi_cap_sizeof(flags);
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pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
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dev->cap_present &= ~QEMU_PCI_CAP_MSI;
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MSI_DEV_PRINTF(dev, "uninit\n");
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}
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void msi_reset(PCIDevice *dev)
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{
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uint16_t flags;
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bool msi64bit;
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if (!msi_present(dev)) {
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return;
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}
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flags = pci_get_word(dev->config + msi_flags_off(dev));
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flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
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msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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pci_set_word(dev->config + msi_flags_off(dev), flags);
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pci_set_long(dev->config + msi_address_lo_off(dev), 0);
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if (msi64bit) {
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pci_set_long(dev->config + msi_address_hi_off(dev), 0);
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}
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pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
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if (flags & PCI_MSI_FLAGS_MASKBIT) {
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pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
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pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
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}
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MSI_DEV_PRINTF(dev, "reset\n");
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}
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static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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uint32_t mask, data;
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bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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assert(vector < PCI_MSI_VECTORS_MAX);
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if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
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return false;
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}
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data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
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if (xen_is_pirq_msi(data)) {
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return false;
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}
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mask = pci_get_long(dev->config +
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msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
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return mask & (1U << vector);
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}
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void msi_notify(PCIDevice *dev, unsigned int vector)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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unsigned int nr_vectors = msi_nr_vectors(flags);
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MSIMessage msg;
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assert(vector < nr_vectors);
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if (msi_is_masked(dev, vector)) {
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assert(flags & PCI_MSI_FLAGS_MASKBIT);
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pci_long_test_and_set_mask(
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dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
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MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
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return;
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}
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msg = msi_get_message(dev, vector);
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MSI_DEV_PRINTF(dev,
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"notify vector 0x%x"
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" address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
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vector, msg.address, msg.data);
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msi_send_message(dev, msg);
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}
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void msi_send_message(PCIDevice *dev, MSIMessage msg)
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{
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MemTxAttrs attrs = {};
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attrs.requester_id = pci_requester_id(dev);
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address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
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attrs, NULL);
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}
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/* Normally called by pci_default_write_config(). */
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void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
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unsigned int nr_vectors;
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uint8_t log_num_vecs;
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uint8_t log_max_vecs;
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unsigned int vector;
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uint32_t pending;
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if (!msi_present(dev) ||
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!ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
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return;
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}
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#ifdef MSI_DEBUG
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MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
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addr, val, len);
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MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
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flags,
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pci_get_long(dev->config + msi_address_lo_off(dev)));
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if (msi64bit) {
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fprintf(stderr, " address-hi: 0x%"PRIx32,
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pci_get_long(dev->config + msi_address_hi_off(dev)));
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}
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fprintf(stderr, " data: 0x%"PRIx16,
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pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
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if (flags & PCI_MSI_FLAGS_MASKBIT) {
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fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
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pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
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pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
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}
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fprintf(stderr, "\n");
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#endif
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if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
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return;
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}
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/*
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* Now MSI is enabled, clear INTx# interrupts.
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* the driver is prohibited from writing enable bit to mask
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* a service request. But the guest OS could do this.
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* So we just discard the interrupts as moderate fallback.
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*
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* 6.8.3.3. Enabling Operation
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* While enabled for MSI or MSI-X operation, a function is prohibited
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* from using its INTx# pin (if implemented) to request
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* service (MSI, MSI-X, and INTx# are mutually exclusive).
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*/
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pci_device_deassert_intx(dev);
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/*
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* nr_vectors might be set bigger than capable. So clamp it.
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* This is not legal by spec, so we can do anything we like,
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* just don't crash the host
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*/
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log_num_vecs =
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(flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
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log_max_vecs =
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(flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
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if (log_num_vecs > log_max_vecs) {
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flags &= ~PCI_MSI_FLAGS_QSIZE;
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flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
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pci_set_word(dev->config + msi_flags_off(dev), flags);
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}
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if (!msi_per_vector_mask) {
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/* if per vector masking isn't supported,
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there is no pending interrupt. */
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return;
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}
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nr_vectors = msi_nr_vectors(flags);
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/* This will discard pending interrupts, if any. */
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pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
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pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
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pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
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/* deliver pending interrupts which are unmasked */
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for (vector = 0; vector < nr_vectors; ++vector) {
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if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
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continue;
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}
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pci_long_test_and_clear_mask(
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dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
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msi_notify(dev, vector);
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}
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}
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unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
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{
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uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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return msi_nr_vectors(flags);
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}
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