A few machines need to translate the ELF header addresses into physical addresses. Currently the only possibility is to add a value to the addresses. This patch replaces the addend argument by and a translation function and an opaque passed to the function. A NULL function does not translate the address. The patch also convert all machines that have an addend, simplify the PowerPC kernel loading and fix the MIPS kernel loading using this new feature. Other machines may benefit from this feature. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
309 lines
8.6 KiB
C
309 lines
8.6 KiB
C
/*
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* QEMU/MIPS pseudo-board
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*
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* emulates a simple machine with ISA-like bus.
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* ISA IO space mapped to the 0x14000000 (PHYS) and
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* ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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* All peripherial devices are attached to this "bus" with
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* the standard PC ISA addresses.
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*/
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#include "hw.h"
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#include "mips.h"
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#include "pc.h"
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#include "isa.h"
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#include "net.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "flash.h"
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#include "qemu-log.h"
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#include "mips-bios.h"
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#include "ide.h"
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#include "loader.h"
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#include "elf.h"
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#define MAX_IDE_BUS 2
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static PITState *pit; /* PIT i8254 */
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/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
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static struct _loaderparams {
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int ram_size;
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const char *kernel_filename;
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const char *kernel_cmdline;
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const char *initrd_filename;
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} loaderparams;
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static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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if ((addr & 0xffff) == 0 && val == 42)
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qemu_system_reset_request ();
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else if ((addr & 0xffff) == 4 && val == 42)
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qemu_system_shutdown_request ();
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}
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static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc * const mips_qemu_write[] = {
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&mips_qemu_writel,
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&mips_qemu_writel,
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&mips_qemu_writel,
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};
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static CPUReadMemoryFunc * const mips_qemu_read[] = {
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&mips_qemu_readl,
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&mips_qemu_readl,
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&mips_qemu_readl,
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};
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static int mips_qemu_iomemtype = 0;
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typedef struct ResetData {
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CPUState *env;
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uint64_t vector;
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} ResetData;
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static int64_t load_kernel(void)
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{
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int64_t entry, kernel_high;
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long kernel_size, initrd_size, params_size;
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ram_addr_t initrd_offset;
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uint32_t *params_buf;
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int big_endian;
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#ifdef TARGET_WORDS_BIGENDIAN
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big_endian = 1;
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#else
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big_endian = 0;
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#endif
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kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
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NULL, (uint64_t *)&entry, NULL,
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(uint64_t *)&kernel_high, big_endian,
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ELF_MACHINE, 1);
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if (kernel_size >= 0) {
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if ((entry & ~0x7fffffffULL) == 0x80000000)
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entry = (int32_t)entry;
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} else {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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loaderparams.kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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initrd_offset = 0;
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if (loaderparams.initrd_filename) {
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initrd_size = get_image_size (loaderparams.initrd_filename);
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if (initrd_size > 0) {
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initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
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if (initrd_offset + initrd_size > ram_size) {
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fprintf(stderr,
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"qemu: memory too small for initial ram disk '%s'\n",
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loaderparams.initrd_filename);
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exit(1);
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}
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initrd_size = load_image_targphys(loaderparams.initrd_filename,
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initrd_offset,
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ram_size - initrd_offset);
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}
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if (initrd_size == (target_ulong) -1) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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loaderparams.initrd_filename);
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exit(1);
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}
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}
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/* Store command line. */
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params_size = 264;
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params_buf = qemu_malloc(params_size);
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params_buf[0] = tswap32(ram_size);
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params_buf[1] = tswap32(0x12345678);
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if (initrd_size > 0) {
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snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s",
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cpu_mips_phys_to_kseg0(NULL, initrd_offset),
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initrd_size, loaderparams.kernel_cmdline);
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} else {
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snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
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}
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rom_add_blob_fixed("params", params_buf, params_size,
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(16 << 20) - 264);
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return entry;
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}
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUState *env = s->env;
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cpu_reset(env);
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env->active_tc.PC = s->vector;
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}
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static const int sector_len = 32 * 1024;
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static
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void mips_r4k_init (ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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char *filename;
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ram_addr_t ram_offset;
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ram_addr_t bios_offset;
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int bios_size;
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CPUState *env;
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ResetData *reset_info;
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RTCState *rtc_state;
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int i;
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qemu_irq *i8259;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *dinfo;
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/* init CPUs */
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "R4000";
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#else
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cpu_model = "24Kf";
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#endif
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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reset_info = qemu_mallocz(sizeof(ResetData));
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reset_info->env = env;
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reset_info->vector = env->active_tc.PC;
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qemu_register_reset(main_cpu_reset, reset_info);
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/* allocate RAM */
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if (ram_size > (256 << 20)) {
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fprintf(stderr,
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"qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
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((unsigned int)ram_size / (1 << 20)));
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exit(1);
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}
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ram_offset = qemu_ram_alloc(ram_size);
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cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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if (!mips_qemu_iomemtype) {
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mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
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mips_qemu_write, NULL);
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}
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cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
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/* Try to load a BIOS image. If this fails, we continue regardless,
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but initialize the hardware ourselves. When a kernel gets
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preloaded we also initialize the hardware, since the BIOS wasn't
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run. */
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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bios_size = get_image_size(filename);
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} else {
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bios_size = -1;
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}
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if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
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bios_offset = qemu_ram_alloc(BIOS_SIZE);
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cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
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bios_offset | IO_MEM_ROM);
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load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
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} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
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uint32_t mips_rom = 0x00400000;
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bios_offset = qemu_ram_alloc(mips_rom);
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if (!pflash_cfi01_register(0x1fc00000, bios_offset,
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dinfo->bdrv, sector_len, mips_rom / sector_len,
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4, 0, 0, 0, 0)) {
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fprintf(stderr, "qemu: Error registering flash memory.\n");
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}
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}
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else {
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/* not fatal */
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fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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bios_name);
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}
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if (filename) {
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qemu_free(filename);
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}
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if (kernel_filename) {
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loaderparams.ram_size = ram_size;
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loaderparams.kernel_filename = kernel_filename;
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loaderparams.kernel_cmdline = kernel_cmdline;
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loaderparams.initrd_filename = initrd_filename;
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reset_info->vector = load_kernel();
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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/* The PIC is attached to the MIPS CPU INT0 pin */
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i8259 = i8259_init(env->irq[2]);
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isa_bus_new(NULL);
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isa_bus_irqs(i8259);
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rtc_state = rtc_init(2000);
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/* Register 64 KB of ISA IO space at 0x14000000 */
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isa_mmio_init(0x14000000, 0x00010000);
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isa_mem_base = 0x10000000;
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pit = pit_init(0x40, i8259[0]);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_isa_init(i, serial_hds[i]);
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}
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}
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isa_vga_init();
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if (nd_table[0].vlan)
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isa_ne2000_init(0x300, 9, &nd_table[0]);
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if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
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fprintf(stderr, "qemu: too many IDE bus\n");
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exit(1);
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}
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for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
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hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
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}
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for(i = 0; i < MAX_IDE_BUS; i++)
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isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
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hd[MAX_IDE_DEVS * i],
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hd[MAX_IDE_DEVS * i + 1]);
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isa_create_simple("i8042");
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}
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static QEMUMachine mips_machine = {
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.name = "mips",
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.desc = "mips r4k platform",
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.init = mips_r4k_init,
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};
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static void mips_machine_init(void)
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{
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qemu_register_machine(&mips_machine);
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}
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machine_init(mips_machine_init);
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