Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
480 lines
13 KiB
C
480 lines
13 KiB
C
/*
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* QTest testcase for e1000e NIC
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*
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include <glib.h>
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#include "libqtest.h"
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#include "qemu-common.h"
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#include "libqos/pci-pc.h"
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#include "qemu/sockets.h"
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#include "qemu/iov.h"
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#include "qemu/bitops.h"
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#include "libqos/malloc.h"
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#include "libqos/malloc-pc.h"
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#include "libqos/malloc-generic.h"
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#define E1000E_IMS (0x00d0)
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#define E1000E_STATUS (0x0008)
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#define E1000E_STATUS_LU BIT(1)
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#define E1000E_STATUS_ASDV1000 BIT(9)
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#define E1000E_CTRL (0x0000)
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#define E1000E_CTRL_RESET BIT(26)
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#define E1000E_RCTL (0x0100)
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#define E1000E_RCTL_EN BIT(1)
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#define E1000E_RCTL_UPE BIT(3)
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#define E1000E_RCTL_MPE BIT(4)
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#define E1000E_RFCTL (0x5008)
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#define E1000E_RFCTL_EXTEN BIT(15)
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#define E1000E_TCTL (0x0400)
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#define E1000E_TCTL_EN BIT(1)
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#define E1000E_CTRL_EXT (0x0018)
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#define E1000E_CTRL_EXT_DRV_LOAD BIT(28)
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#define E1000E_CTRL_EXT_TXLSFLOW BIT(22)
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#define E1000E_RX0_MSG_ID (0)
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#define E1000E_TX0_MSG_ID (1)
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#define E1000E_OTHER_MSG_ID (2)
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#define E1000E_IVAR (0x00E4)
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#define E1000E_IVAR_TEST_CFG ((E1000E_RX0_MSG_ID << 0) | BIT(3) | \
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(E1000E_TX0_MSG_ID << 8) | BIT(11) | \
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(E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
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BIT(31))
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#define E1000E_RING_LEN (0x1000)
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#define E1000E_TXD_LEN (16)
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#define E1000E_RXD_LEN (16)
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#define E1000E_TDBAL (0x3800)
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#define E1000E_TDBAH (0x3804)
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#define E1000E_TDLEN (0x3808)
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#define E1000E_TDH (0x3810)
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#define E1000E_TDT (0x3818)
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#define E1000E_RDBAL (0x2800)
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#define E1000E_RDBAH (0x2804)
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#define E1000E_RDLEN (0x2808)
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#define E1000E_RDH (0x2810)
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#define E1000E_RDT (0x2818)
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typedef struct e1000e_device {
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QPCIDevice *pci_dev;
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void *mac_regs;
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uint64_t tx_ring;
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uint64_t rx_ring;
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} e1000e_device;
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static int test_sockets[2];
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static QGuestAllocator *test_alloc;
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static QPCIBus *test_bus;
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static void e1000e_pci_foreach_callback(QPCIDevice *dev, int devfn, void *data)
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{
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*(QPCIDevice **) data = dev;
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}
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static QPCIDevice *e1000e_device_find(QPCIBus *bus)
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{
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static const int e1000e_vendor_id = 0x8086;
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static const int e1000e_dev_id = 0x10D3;
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QPCIDevice *e1000e_dev = NULL;
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qpci_device_foreach(bus, e1000e_vendor_id, e1000e_dev_id,
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e1000e_pci_foreach_callback, &e1000e_dev);
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g_assert_nonnull(e1000e_dev);
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return e1000e_dev;
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}
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static void e1000e_macreg_write(e1000e_device *d, uint32_t reg, uint32_t val)
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{
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qpci_io_writel(d->pci_dev, d->mac_regs + reg, val);
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}
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static uint32_t e1000e_macreg_read(e1000e_device *d, uint32_t reg)
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{
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return qpci_io_readl(d->pci_dev, d->mac_regs + reg);
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}
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static void e1000e_device_init(QPCIBus *bus, e1000e_device *d)
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{
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uint32_t val;
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d->pci_dev = e1000e_device_find(bus);
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/* Enable the device */
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qpci_device_enable(d->pci_dev);
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/* Map BAR0 (mac registers) */
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d->mac_regs = qpci_iomap(d->pci_dev, 0, NULL);
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g_assert_nonnull(d->mac_regs);
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/* Reset the device */
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val = e1000e_macreg_read(d, E1000E_CTRL);
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e1000e_macreg_write(d, E1000E_CTRL, val | E1000E_CTRL_RESET);
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/* Enable and configure MSI-X */
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qpci_msix_enable(d->pci_dev);
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e1000e_macreg_write(d, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
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/* Check the device status - link and speed */
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val = e1000e_macreg_read(d, E1000E_STATUS);
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g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
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==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
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/* Initialize TX/RX logic */
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e1000e_macreg_write(d, E1000E_RCTL, 0);
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e1000e_macreg_write(d, E1000E_TCTL, 0);
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/* Notify the device that the driver is ready */
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val = e1000e_macreg_read(d, E1000E_CTRL_EXT);
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e1000e_macreg_write(d, E1000E_CTRL_EXT,
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val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
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/* Allocate and setup TX ring */
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d->tx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
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g_assert(d->tx_ring != 0);
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e1000e_macreg_write(d, E1000E_TDBAL, (uint32_t) d->tx_ring);
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e1000e_macreg_write(d, E1000E_TDBAH, (uint32_t) (d->tx_ring >> 32));
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e1000e_macreg_write(d, E1000E_TDLEN, E1000E_RING_LEN);
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e1000e_macreg_write(d, E1000E_TDT, 0);
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e1000e_macreg_write(d, E1000E_TDH, 0);
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/* Enable transmit */
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e1000e_macreg_write(d, E1000E_TCTL, E1000E_TCTL_EN);
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/* Allocate and setup RX ring */
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d->rx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
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g_assert(d->rx_ring != 0);
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e1000e_macreg_write(d, E1000E_RDBAL, (uint32_t)d->rx_ring);
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e1000e_macreg_write(d, E1000E_RDBAH, (uint32_t)(d->rx_ring >> 32));
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e1000e_macreg_write(d, E1000E_RDLEN, E1000E_RING_LEN);
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e1000e_macreg_write(d, E1000E_RDT, 0);
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e1000e_macreg_write(d, E1000E_RDH, 0);
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/* Enable receive */
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e1000e_macreg_write(d, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
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e1000e_macreg_write(d, E1000E_RCTL, E1000E_RCTL_EN |
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E1000E_RCTL_UPE |
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E1000E_RCTL_MPE);
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/* Enable all interrupts */
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e1000e_macreg_write(d, E1000E_IMS, 0xFFFFFFFF);
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}
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static void e1000e_tx_ring_push(e1000e_device *d, void *descr)
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{
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uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
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uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
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memwrite(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
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e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
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/* Read WB data for the packet transmitted */
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memread(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
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}
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static void e1000e_rx_ring_push(e1000e_device *d, void *descr)
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{
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uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
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uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
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memwrite(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
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e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
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/* Read WB data for the packet received */
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memread(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
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}
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static void e1000e_wait_isr(e1000e_device *d, uint16_t msg_id)
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{
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guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
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do {
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if (qpci_msix_pending(d->pci_dev, msg_id)) {
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return;
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}
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clock_step(10000);
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} while (g_get_monotonic_time() < end_time);
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g_error("Timeout expired");
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}
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static void e1000e_send_verify(e1000e_device *d)
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{
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struct {
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uint64_t buffer_addr;
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union {
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uint32_t data;
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struct {
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uint16_t length;
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uint8_t cso;
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uint8_t cmd;
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} flags;
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} lower;
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union {
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uint32_t data;
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struct {
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uint8_t status;
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uint8_t css;
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uint16_t special;
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} fields;
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} upper;
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} descr;
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static const uint32_t dtyp_data = BIT(20);
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static const uint32_t dtyp_ext = BIT(29);
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static const uint32_t dcmd_rs = BIT(27);
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static const uint32_t dcmd_eop = BIT(24);
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static const uint32_t dsta_dd = BIT(0);
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static const int data_len = 64;
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char buffer[64];
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int ret;
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uint32_t recv_len;
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/* Prepare test data buffer */
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uint64_t data = guest_alloc(test_alloc, data_len);
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memwrite(data, "TEST", 5);
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/* Prepare TX descriptor */
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memset(&descr, 0, sizeof(descr));
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descr.buffer_addr = cpu_to_le64(data);
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descr.lower.data = cpu_to_le32(dcmd_rs |
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dcmd_eop |
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dtyp_ext |
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dtyp_data |
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data_len);
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/* Put descriptor to the ring */
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e1000e_tx_ring_push(d, &descr);
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/* Wait for TX WB interrupt */
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e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
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/* Check DD bit */
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g_assert_cmphex(le32_to_cpu(descr.upper.data) & dsta_dd, ==, dsta_dd);
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/* Check data sent to the backend */
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ret = qemu_recv(test_sockets[0], &recv_len, sizeof(recv_len), 0);
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g_assert_cmpint(ret, == , sizeof(recv_len));
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qemu_recv(test_sockets[0], buffer, 64, 0);
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g_assert_cmpstr(buffer, == , "TEST");
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/* Free test data buffer */
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guest_free(test_alloc, data);
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}
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static void e1000e_receive_verify(e1000e_device *d)
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{
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union {
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struct {
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uint64_t buffer_addr;
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uint64_t reserved;
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} read;
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struct {
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struct {
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uint32_t mrq;
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union {
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uint32_t rss;
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struct {
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uint16_t ip_id;
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uint16_t csum;
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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uint32_t status_error;
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uint16_t length;
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uint16_t vlan;
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} upper;
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} wb;
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} descr;
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static const uint32_t esta_dd = BIT(0);
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char test[] = "TEST";
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int len = htonl(sizeof(test));
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struct iovec iov[] = {
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{
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.iov_base = &len,
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.iov_len = sizeof(len),
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},{
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.iov_base = test,
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.iov_len = sizeof(test),
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},
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};
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static const int data_len = 64;
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char buffer[64];
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int ret;
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/* Send a dummy packet to device's socket*/
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ret = iov_send(test_sockets[0], iov, 2, 0, sizeof(len) + sizeof(test));
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g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
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/* Prepare test data buffer */
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uint64_t data = guest_alloc(test_alloc, data_len);
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/* Prepare RX descriptor */
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memset(&descr, 0, sizeof(descr));
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descr.read.buffer_addr = cpu_to_le64(data);
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/* Put descriptor to the ring */
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e1000e_rx_ring_push(d, &descr);
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/* Wait for TX WB interrupt */
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e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
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/* Check DD bit */
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g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
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esta_dd, ==, esta_dd);
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/* Check data sent to the backend */
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memread(data, buffer, sizeof(buffer));
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g_assert_cmpstr(buffer, == , "TEST");
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/* Free test data buffer */
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guest_free(test_alloc, data);
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}
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static void e1000e_device_clear(QPCIBus *bus, e1000e_device *d)
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{
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qpci_iounmap(d->pci_dev, d->mac_regs);
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qpci_msix_disable(d->pci_dev);
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}
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static void data_test_init(e1000e_device *d)
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{
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char *cmdline;
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int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
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g_assert_cmpint(ret, != , -1);
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cmdline = g_strdup_printf("-netdev socket,fd=%d,id=hs0 "
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"-device e1000e,netdev=hs0", test_sockets[1]);
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g_assert_nonnull(cmdline);
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qtest_start(cmdline);
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g_free(cmdline);
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test_bus = qpci_init_pc();
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g_assert_nonnull(test_bus);
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test_alloc = pc_alloc_init();
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g_assert_nonnull(test_alloc);
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e1000e_device_init(test_bus, d);
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}
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static void data_test_clear(e1000e_device *d)
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{
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e1000e_device_clear(test_bus, d);
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close(test_sockets[0]);
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pc_alloc_uninit(test_alloc);
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qpci_free_pc(test_bus);
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qtest_end();
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}
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static void test_e1000e_init(gconstpointer data)
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{
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e1000e_device d;
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data_test_init(&d);
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data_test_clear(&d);
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}
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static void test_e1000e_tx(gconstpointer data)
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{
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e1000e_device d;
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data_test_init(&d);
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e1000e_send_verify(&d);
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data_test_clear(&d);
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}
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static void test_e1000e_rx(gconstpointer data)
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{
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e1000e_device d;
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data_test_init(&d);
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e1000e_receive_verify(&d);
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data_test_clear(&d);
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}
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static void test_e1000e_multiple_transfers(gconstpointer data)
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{
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static const long iterations = 4 * 1024;
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long i;
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e1000e_device d;
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data_test_init(&d);
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for (i = 0; i < iterations; i++) {
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e1000e_send_verify(&d);
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e1000e_receive_verify(&d);
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}
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data_test_clear(&d);
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}
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static void test_e1000e_hotplug(gconstpointer data)
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{
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static const uint8_t slot = 0x06;
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qtest_start("-device e1000e");
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qpci_plug_device_test("e1000e", "e1000e_net", slot, NULL);
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qpci_unplug_acpi_device_test("e1000e_net", slot);
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qtest_end();
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_data_func("e1000e/init", NULL, test_e1000e_init);
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qtest_add_data_func("e1000e/tx", NULL, test_e1000e_tx);
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qtest_add_data_func("e1000e/rx", NULL, test_e1000e_rx);
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qtest_add_data_func("e1000e/multiple_transfers", NULL,
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test_e1000e_multiple_transfers);
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qtest_add_data_func("e1000e/hotplug", NULL, test_e1000e_hotplug);
|
|
|
|
return g_test_run();
|
|
}
|