Callers of dma_blk_io have no way to pass extra data to the DMAIOFunc, because the original callback and opaque are gone by the time DMAIOFunc is called. On the other hand, the BlockBackend is usually derived from those extra data that you could pass to the DMAIOFunc (in the next patch, that would be the SCSIRequest). So change DMAIOFunc's prototype, decoupling it from blk_aio_readv and blk_aio_writev's. The new prototype loses the BlockBackend and gains an extra opaque value which, in the case of dma_blk_readv and dma_blk_writev, is of course used for the BlockBackend. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
640 lines
17 KiB
C
640 lines
17 KiB
C
/*
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* QEMU IDE Emulation: MacIO support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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#include "hw/ppc/mac_dbdma.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/dma.h"
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#include <hw/ide/internal.h>
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/* debug MACIO */
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// #define DEBUG_MACIO
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#ifdef DEBUG_MACIO
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static const int debug_macio = 1;
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#else
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static const int debug_macio = 0;
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#endif
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#define MACIO_DPRINTF(fmt, ...) do { \
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if (debug_macio) { \
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printf(fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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#define MACIO_PAGE_SIZE 4096
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/*
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* Unaligned DMA read/write access functions required for OS X/Darwin which
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* don't perform DMA transactions on sector boundaries. These functions are
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* modelled on bdrv_co_preadv()/bdrv_co_pwritev() and so should be easy to
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* remove if the unaligned block APIs are ever exposed.
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*/
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static void pmac_dma_read(BlockBackend *blk,
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int64_t offset, unsigned int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr, dma_len;
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void *mem;
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int64_t sector_num;
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int nsector;
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uint64_t align = BDRV_SECTOR_SIZE;
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size_t head_bytes, tail_bytes;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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sector_num = (offset >> 9);
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nsector = (io->len >> 9);
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MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
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"sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
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sector_num, nsector);
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dma_addr = io->addr;
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dma_len = io->len;
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mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
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DMA_DIRECTION_FROM_DEVICE);
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if (offset & (align - 1)) {
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head_bytes = offset & (align - 1);
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MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
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"discarding %zu bytes\n", sector_num, head_bytes);
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qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
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bytes += offset & (align - 1);
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offset = offset & ~(align - 1);
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}
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qemu_iovec_add(&io->iov, mem, io->len);
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if ((offset + bytes) & (align - 1)) {
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tail_bytes = (offset + bytes) & (align - 1);
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MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
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"discarding bytes %zu\n", sector_num, tail_bytes);
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qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
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bytes = ROUND_UP(bytes, align);
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}
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
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"nsector: %x\n", (offset >> 9), (bytes >> 9));
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s->bus->dma->aiocb = blk_aio_preadv(blk, offset, &io->iov, 0, cb, io);
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}
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static void pmac_dma_write(BlockBackend *blk,
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int64_t offset, int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr, dma_len;
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void *mem;
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int64_t sector_num;
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int nsector;
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uint64_t align = BDRV_SECTOR_SIZE;
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size_t head_bytes, tail_bytes;
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bool unaligned_head = false, unaligned_tail = false;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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sector_num = (offset >> 9);
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nsector = (io->len >> 9);
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MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
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"sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
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sector_num, nsector);
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dma_addr = io->addr;
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dma_len = io->len;
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mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
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DMA_DIRECTION_TO_DEVICE);
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if (offset & (align - 1)) {
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head_bytes = offset & (align - 1);
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sector_num = ((offset & ~(align - 1)) >> 9);
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MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
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PRId64 "\n", sector_num);
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blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
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qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
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qemu_iovec_add(&io->iov, mem, io->len);
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bytes += offset & (align - 1);
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offset = offset & ~(align - 1);
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unaligned_head = true;
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}
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if ((offset + bytes) & (align - 1)) {
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tail_bytes = (offset + bytes) & (align - 1);
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sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
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MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
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PRId64 "\n", sector_num);
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blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
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if (!unaligned_head) {
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qemu_iovec_add(&io->iov, mem, io->len);
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}
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qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
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align - tail_bytes);
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bytes = ROUND_UP(bytes, align);
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unaligned_tail = true;
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}
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if (!unaligned_head && !unaligned_tail) {
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qemu_iovec_add(&io->iov, mem, io->len);
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}
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
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"nsector: %x\n", (offset >> 9), (bytes >> 9));
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s->bus->dma->aiocb = blk_aio_pwritev(blk, offset, &io->iov, 0, cb, io);
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}
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static void pmac_dma_trim(BlockBackend *blk,
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int64_t offset, int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr, dma_len;
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void *mem;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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dma_addr = io->addr;
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dma_len = io->len;
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mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
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DMA_DIRECTION_TO_DEVICE);
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qemu_iovec_add(&io->iov, mem, io->len);
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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s->bus->dma->aiocb = ide_issue_trim(offset, &io->iov, cb, io, blk);
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}
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int64_t offset;
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MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
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if (ret < 0) {
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MACIO_DPRINTF("DMA error: %d\n", ret);
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ide_atapi_io_error(s, ret);
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goto done;
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}
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if (!m->dma_active) {
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MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
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s->nsector, io->len, s->status);
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/* data not ready yet, wait for the channel to get restarted */
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io->processing = false;
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return;
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}
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if (s->io_buffer_size <= 0) {
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MACIO_DPRINTF("End of IDE transfer\n");
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ide_atapi_cmd_ok(s);
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m->dma_active = false;
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goto done;
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}
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if (io->len == 0) {
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MACIO_DPRINTF("End of DMA transfer\n");
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goto done;
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}
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if (s->lba == -1) {
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/* Non-block ATAPI transfer - just copy to RAM */
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s->io_buffer_size = MIN(s->io_buffer_size, io->len);
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cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
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ide_atapi_cmd_ok(s);
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m->dma_active = false;
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goto done;
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}
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/* Calculate current offset */
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offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
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pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
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return;
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done:
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if (ret < 0) {
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block_acct_failed(blk_get_stats(s->blk), &s->acct);
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} else {
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block_acct_done(blk_get_stats(s->blk), &s->acct);
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}
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ide_set_inactive(s, false);
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io->dma_end(opaque);
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}
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static void pmac_ide_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int64_t offset;
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MACIO_DPRINTF("pmac_ide_transfer_cb\n");
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if (ret < 0) {
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MACIO_DPRINTF("DMA error: %d\n", ret);
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ide_dma_error(s);
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goto done;
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}
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if (!m->dma_active) {
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MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
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s->nsector, io->len, s->status);
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/* data not ready yet, wait for the channel to get restarted */
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io->processing = false;
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return;
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}
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if (s->io_buffer_size <= 0) {
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MACIO_DPRINTF("End of IDE transfer\n");
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s->bus);
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m->dma_active = false;
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goto done;
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}
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if (io->len == 0) {
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MACIO_DPRINTF("End of DMA transfer\n");
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goto done;
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}
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/* Calculate number of sectors */
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offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_WRITE:
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pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_TRIM:
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pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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break;
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default:
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abort();
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}
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return;
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done:
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if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
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if (ret < 0) {
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block_acct_failed(blk_get_stats(s->blk), &s->acct);
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} else {
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block_acct_done(blk_get_stats(s->blk), &s->acct);
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}
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}
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ide_set_inactive(s, false);
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io->dma_end(opaque);
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}
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static void pmac_ide_transfer(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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MACIO_DPRINTF("\n");
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if (s->drive_kind == IDE_CD) {
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block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
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BLOCK_ACCT_READ);
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pmac_ide_atapi_transfer_cb(io, 0);
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return;
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}
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
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BLOCK_ACCT_READ);
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break;
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case IDE_DMA_WRITE:
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block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
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BLOCK_ACCT_WRITE);
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break;
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default:
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break;
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}
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pmac_ide_transfer_cb(io, 0);
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}
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static void pmac_ide_flush(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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if (s->bus->dma->aiocb) {
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blk_drain_all();
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}
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}
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/* PowerMac IDE memory IO */
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static void pmac_ide_writeb (void *opaque,
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hwaddr addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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ide_ioport_write(&d->bus, addr, val);
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break;
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case 8:
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case 22:
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ide_cmd_write(&d->bus, 0, val);
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break;
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default:
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break;
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}
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}
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static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
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{
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uint8_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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retval = ide_ioport_read(&d->bus, addr);
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break;
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case 8:
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case 22:
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retval = ide_status_read(&d->bus, 0);
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break;
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default:
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retval = 0xFF;
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break;
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}
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return retval;
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}
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static void pmac_ide_writew (void *opaque,
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hwaddr addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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val = bswap16(val);
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if (addr == 0) {
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ide_data_writew(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
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{
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uint16_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readw(&d->bus, 0);
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} else {
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retval = 0xFFFF;
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}
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retval = bswap16(retval);
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return retval;
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}
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static void pmac_ide_writel (void *opaque,
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hwaddr addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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val = bswap32(val);
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if (addr == 0) {
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ide_data_writel(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
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{
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uint32_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readl(&d->bus, 0);
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} else {
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retval = 0xFFFFFFFF;
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}
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retval = bswap32(retval);
|
|
return retval;
|
|
}
|
|
|
|
static const MemoryRegionOps pmac_ide_ops = {
|
|
.old_mmio = {
|
|
.write = {
|
|
pmac_ide_writeb,
|
|
pmac_ide_writew,
|
|
pmac_ide_writel,
|
|
},
|
|
.read = {
|
|
pmac_ide_readb,
|
|
pmac_ide_readw,
|
|
pmac_ide_readl,
|
|
},
|
|
},
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_pmac = {
|
|
.name = "ide",
|
|
.version_id = 4,
|
|
.minimum_version_id = 0,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_IDE_BUS(bus, MACIOIDEState),
|
|
VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
|
|
VMSTATE_BOOL(dma_active, MACIOIDEState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void macio_ide_reset(DeviceState *dev)
|
|
{
|
|
MACIOIDEState *d = MACIO_IDE(dev);
|
|
|
|
ide_bus_reset(&d->bus);
|
|
}
|
|
|
|
static int ide_nop_int(IDEDMA *dma, int x)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
|
|
BlockCompletionFunc *cb)
|
|
{
|
|
MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
|
|
|
|
s->io_buffer_index = 0;
|
|
if (s->drive_kind == IDE_CD) {
|
|
s->io_buffer_size = s->packet_transfer_size;
|
|
} else {
|
|
s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
|
|
}
|
|
|
|
MACIO_DPRINTF("\n\n------------ IDE transfer\n");
|
|
MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
|
|
s->io_buffer_size, s->io_buffer_index);
|
|
MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
|
|
MACIO_DPRINTF("-------------------------\n");
|
|
|
|
m->dma_active = true;
|
|
DBDMA_kick(m->dbdma);
|
|
}
|
|
|
|
static const IDEDMAOps dbdma_ops = {
|
|
.start_dma = ide_dbdma_start,
|
|
.prepare_buf = ide_nop_int32,
|
|
.rw_buf = ide_nop_int,
|
|
};
|
|
|
|
static void macio_ide_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
MACIOIDEState *s = MACIO_IDE(dev);
|
|
|
|
ide_init2(&s->bus, s->irq);
|
|
|
|
/* Register DMA callbacks */
|
|
s->dma.ops = &dbdma_ops;
|
|
s->bus.dma = &s->dma;
|
|
}
|
|
|
|
static void macio_ide_initfn(Object *obj)
|
|
{
|
|
SysBusDevice *d = SYS_BUS_DEVICE(obj);
|
|
MACIOIDEState *s = MACIO_IDE(obj);
|
|
|
|
ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
|
|
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
|
|
sysbus_init_mmio(d, &s->mem);
|
|
sysbus_init_irq(d, &s->irq);
|
|
sysbus_init_irq(d, &s->dma_irq);
|
|
}
|
|
|
|
static void macio_ide_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = macio_ide_realizefn;
|
|
dc->reset = macio_ide_reset;
|
|
dc->vmsd = &vmstate_pmac;
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo macio_ide_type_info = {
|
|
.name = TYPE_MACIO_IDE,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MACIOIDEState),
|
|
.instance_init = macio_ide_initfn,
|
|
.class_init = macio_ide_class_init,
|
|
};
|
|
|
|
static void macio_ide_register_types(void)
|
|
{
|
|
type_register_static(&macio_ide_type_info);
|
|
}
|
|
|
|
/* hd_table must contain 2 block drivers */
|
|
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
if (hd_table[i]) {
|
|
ide_create_drive(&s->bus, i, hd_table[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
|
|
{
|
|
s->dbdma = dbdma;
|
|
DBDMA_register_channel(dbdma, channel, s->dma_irq,
|
|
pmac_ide_transfer, pmac_ide_flush, s);
|
|
}
|
|
|
|
type_init(macio_ide_register_types)
|