If the migration occurs after the IDE DMA has been set up but before it has been initiated, the state gets lost upon save/restore. Specifically, ->dma_cb callback gets cleared, so, when the guest eventually starts bus mastering, the DMA never completes, causing the guest to time out the operation. OTOH all the infrastructure is already in place to restart the DMA if the migration happens while the DMA is in progress. So reuse that infrastructure, by setting bus->error_status based on ->dma_cmd in pre_save if ->dma_cb callback is already set but DMAING is clear. This will indicate the need for restart and make sure ->dma_cb is restored in ide_restart_bh(); howeover since DMAING is clear the state upon restore will be exactly "ready for DMA" as before the save. Signed-off-by: Pavel Butsykin <pbutsykin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1459924806-306-2-git-send-email-den@openvz.org Signed-off-by: John Snow <jsnow@redhat.com>
469 lines
13 KiB
C
469 lines
13 KiB
C
/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include <hw/hw.h>
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#include <hw/i386/pc.h>
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#include <hw/pci/pci.h>
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#include <hw/isa/isa.h>
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#include "sysemu/block-backend.h"
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#include "sysemu/dma.h"
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#include "qemu/error-report.h"
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#include <hw/ide/pci.h>
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#define BMDMA_PAGE_SIZE 4096
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#define BM_MIGRATION_COMPAT_STATUS_BITS \
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(IDE_RETRY_DMA | IDE_RETRY_PIO | \
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IDE_RETRY_READ | IDE_RETRY_FLUSH)
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static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
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BlockCompletionFunc *dma_cb)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->dma_cb = dma_cb;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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if (bm->status & BM_STATUS_DMAING) {
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bm->dma_cb(bmdma_active_if(bm), 0);
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}
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}
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/**
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* Prepare an sglist based on available PRDs.
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* @limit: How many bytes to prepare total.
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*
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* Returns the number of bytes prepared, -1 on error.
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* IDEState.io_buffer_size will contain the number of bytes described
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* by the PRDs, whether or not we added them to the sglist.
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*/
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static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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IDEState *s = bmdma_active_if(bm);
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PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
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struct {
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uint32_t addr;
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uint32_t size;
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} prd;
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int l, len;
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pci_dma_sglist_init(&s->sg, pci_dev,
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s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
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s->io_buffer_size = 0;
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for(;;) {
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if (bm->cur_prd_len == 0) {
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
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return s->sg.size;
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}
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pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr);
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prd.size = le32_to_cpu(prd.size);
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len = prd.size & 0xfffe;
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if (len == 0)
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len = 0x10000;
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bm->cur_prd_len = len;
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bm->cur_prd_addr = prd.addr;
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bm->cur_prd_last = (prd.size & 0x80000000);
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}
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l = bm->cur_prd_len;
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if (l > 0) {
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uint64_t sg_len;
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/* Don't add extra bytes to the SGList; consume any remaining
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* PRDs from the guest, but ignore them. */
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sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
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if (sg_len) {
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qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
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}
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bm->cur_prd_addr += l;
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bm->cur_prd_len -= l;
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s->io_buffer_size += l;
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}
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}
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qemu_sglist_destroy(&s->sg);
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s->io_buffer_size = 0;
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return -1;
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}
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/* return 0 if buffer completed */
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static int bmdma_rw_buf(IDEDMA *dma, int is_write)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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IDEState *s = bmdma_active_if(bm);
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PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
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struct {
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uint32_t addr;
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uint32_t size;
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} prd;
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int l, len;
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for(;;) {
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l = s->io_buffer_size - s->io_buffer_index;
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if (l <= 0)
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break;
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if (bm->cur_prd_len == 0) {
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/* end of table (with a fail safe of one page) */
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if (bm->cur_prd_last ||
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(bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
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return 0;
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pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
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bm->cur_addr += 8;
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prd.addr = le32_to_cpu(prd.addr);
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prd.size = le32_to_cpu(prd.size);
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len = prd.size & 0xfffe;
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if (len == 0)
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len = 0x10000;
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bm->cur_prd_len = len;
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bm->cur_prd_addr = prd.addr;
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bm->cur_prd_last = (prd.size & 0x80000000);
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}
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if (l > bm->cur_prd_len)
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l = bm->cur_prd_len;
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if (l > 0) {
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if (is_write) {
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pci_dma_write(pci_dev, bm->cur_prd_addr,
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s->io_buffer + s->io_buffer_index, l);
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} else {
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pci_dma_read(pci_dev, bm->cur_prd_addr,
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s->io_buffer + s->io_buffer_index, l);
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}
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bm->cur_prd_addr += l;
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bm->cur_prd_len -= l;
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s->io_buffer_index += l;
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}
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}
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return 1;
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}
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static void bmdma_set_inactive(IDEDMA *dma, bool more)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->dma_cb = NULL;
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if (more) {
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bm->status |= BM_STATUS_DMAING;
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} else {
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bm->status &= ~BM_STATUS_DMAING;
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}
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}
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static void bmdma_restart_dma(IDEDMA *dma)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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bm->cur_addr = bm->addr;
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}
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static void bmdma_cancel(BMDMAState *bm)
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{
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if (bm->status & BM_STATUS_DMAING) {
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/* cancel DMA request */
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bmdma_set_inactive(&bm->dma, false);
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}
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}
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static void bmdma_reset(IDEDMA *dma)
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{
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BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
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#ifdef DEBUG_IDE
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printf("ide: dma_reset\n");
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#endif
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bmdma_cancel(bm);
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bm->cmd = 0;
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bm->status = 0;
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bm->addr = 0;
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bm->cur_addr = 0;
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bm->cur_prd_last = 0;
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bm->cur_prd_addr = 0;
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bm->cur_prd_len = 0;
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}
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static void bmdma_irq(void *opaque, int n, int level)
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{
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BMDMAState *bm = opaque;
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if (!level) {
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/* pass through lower */
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qemu_set_irq(bm->irq, level);
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return;
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}
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bm->status |= BM_STATUS_INT;
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/* trigger the real irq */
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qemu_set_irq(bm->irq, level);
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}
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
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{
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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/* Ignore writes to SSBM if it keeps the old value */
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if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
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if (!(val & BM_CMD_START)) {
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ide_cancel_dma_sync(idebus_active_if(bm->bus));
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bm->status &= ~BM_STATUS_DMAING;
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} else {
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bm->cur_addr = bm->addr;
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING;
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bmdma_active_if(bm), 0);
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}
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}
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}
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bm->cmd = val & 0x09;
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}
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static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
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unsigned width)
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{
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BMDMAState *bm = opaque;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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uint64_t data;
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data = (bm->addr >> (addr * 8)) & mask;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data);
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#endif
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return data;
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}
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static void bmdma_addr_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned width)
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{
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BMDMAState *bm = opaque;
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int shift = addr * 8;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data);
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#endif
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bm->addr &= ~(mask << shift);
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bm->addr |= ((data & mask) << shift) & ~3;
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}
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MemoryRegionOps bmdma_addr_ioport_ops = {
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.read = bmdma_addr_read,
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.write = bmdma_addr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static bool ide_bmdma_current_needed(void *opaque)
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{
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BMDMAState *bm = opaque;
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return (bm->cur_prd_len != 0);
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}
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static bool ide_bmdma_status_needed(void *opaque)
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{
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BMDMAState *bm = opaque;
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/* Older versions abused some bits in the status register for internal
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* error state. If any of these bits are set, we must add a subsection to
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* transfer the real status register */
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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return ((bm->status & abused_bits) != 0);
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}
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static void ide_bmdma_pre_save(void *opaque)
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{
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BMDMAState *bm = opaque;
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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if (!(bm->status & BM_STATUS_DMAING) && bm->dma_cb) {
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bm->bus->error_status =
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ide_dma_cmd_to_retry(bmdma_active_if(bm)->dma_cmd);
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}
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bm->migration_retry_unit = bm->bus->retry_unit;
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bm->migration_retry_sector_num = bm->bus->retry_sector_num;
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bm->migration_retry_nsector = bm->bus->retry_nsector;
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bm->migration_compat_status =
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(bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
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}
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/* This function accesses bm->bus->error_status which is loaded only after
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* BMDMA itself. This is why the function is called from ide_pci_post_load
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* instead of being registered with VMState where it would run too early. */
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static int ide_bmdma_post_load(void *opaque, int version_id)
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{
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BMDMAState *bm = opaque;
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uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
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if (bm->status == 0) {
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bm->status = bm->migration_compat_status & ~abused_bits;
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bm->bus->error_status |= bm->migration_compat_status & abused_bits;
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}
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if (bm->bus->error_status) {
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bm->bus->retry_sector_num = bm->migration_retry_sector_num;
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bm->bus->retry_nsector = bm->migration_retry_nsector;
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bm->bus->retry_unit = bm->migration_retry_unit;
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}
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return 0;
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}
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static const VMStateDescription vmstate_bmdma_current = {
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.name = "ide bmdma_current",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = ide_bmdma_current_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cur_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_last, BMDMAState),
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VMSTATE_UINT32(cur_prd_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_len, BMDMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_bmdma_status = {
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.name ="ide bmdma/status",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = ide_bmdma_status_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(status, BMDMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_bmdma = {
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.name = "ide bmdma",
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.version_id = 3,
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.minimum_version_id = 0,
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.pre_save = ide_bmdma_pre_save,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(cmd, BMDMAState),
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VMSTATE_UINT8(migration_compat_status, BMDMAState),
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VMSTATE_UINT32(addr, BMDMAState),
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VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
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VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
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VMSTATE_UINT8(migration_retry_unit, BMDMAState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_bmdma_current,
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&vmstate_bmdma_status,
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NULL
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}
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};
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static int ide_pci_post_load(void *opaque, int version_id)
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{
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PCIIDEState *d = opaque;
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int i;
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for(i = 0; i < 2; i++) {
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/* current versions always store 0/1, but older version
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stored bigger values. We only need last bit */
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d->bmdma[i].migration_retry_unit &= 1;
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ide_bmdma_post_load(&d->bmdma[i], -1);
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}
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return 0;
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}
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const VMStateDescription vmstate_ide_pci = {
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.name = "ide",
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.version_id = 3,
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.minimum_version_id = 0,
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.post_load = ide_pci_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
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VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
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vmstate_bmdma, BMDMAState),
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VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
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VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
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VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
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VMSTATE_END_OF_LIST()
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}
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};
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void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
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{
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PCIIDEState *d = PCI_IDE(dev);
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static const int bus[4] = { 0, 0, 1, 1 };
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static const int unit[4] = { 0, 1, 0, 1 };
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int i;
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for (i = 0; i < 4; i++) {
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if (hd_table[i] == NULL)
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continue;
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ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
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}
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}
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static const struct IDEDMAOps bmdma_ops = {
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.start_dma = bmdma_start_dma,
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.prepare_buf = bmdma_prepare_buf,
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.rw_buf = bmdma_rw_buf,
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.restart_dma = bmdma_restart_dma,
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.set_inactive = bmdma_set_inactive,
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.reset = bmdma_reset,
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};
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void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
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{
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if (bus->dma == &bm->dma) {
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return;
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}
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bm->dma.ops = &bmdma_ops;
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bus->dma = &bm->dma;
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bm->irq = bus->irq;
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bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
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bm->pci_dev = d;
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}
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static const TypeInfo pci_ide_type_info = {
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.name = TYPE_PCI_IDE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIIDEState),
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.abstract = true,
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};
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static void pci_ide_register_types(void)
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{
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type_register_static(&pci_ide_type_info);
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}
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type_init(pci_ide_register_types)
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