haraldwolff/qemu-patch-raspberry4
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qemu-patch-raspberry4/hw/intc
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Peter Maydell 43bbce7fbe hw/intc/armv7m_nvic: Implement cache ID registers 
M profile cores have a similar setup for cache ID registers
to A profile:
 * Cache Level ID Register (CLIDR) is a fixed value
 * Cache Type Register (CTR) is a fixed value
 * Cache Size ID Registers (CCSIDR) are a bank of registers;
   which one you see is selected by the Cache Size Selection
   Register (CSSELR)

The only difference is that they're in the NVIC memory mapped
register space rather than being coprocessor registers.
Implement the M profile view of them.

Since neither Cortex-M3 nor Cortex-M4 implement caches,
we don't need to update their init functions and can leave
the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.
Newer cores (like the Cortex-M33) will want to be able to
set these ID registers to non-zero values, though.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-6-peter.maydell@linaro.org
2018-02-15 18:29:49 +00:00
..
allwinner-a10-pic.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
apic.c apic: add function to apic that will be used by hvf 2017-12-22 15:01:19 +01:00
apic_common.c migration: pre_save return int 2017-09-27 11:35:59 +01:00
arm_gic.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
arm_gic_common.c migration: pre_save return int 2017-09-27 11:35:59 +01:00
arm_gic_kvm.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
arm_gicv2m.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
arm_gicv3.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
arm_gicv3_common.c migration: pre_save return int 2017-09-27 11:35:59 +01:00
arm_gicv3_cpuif.c arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented 2017-06-07 17:21:44 +01:00
arm_gicv3_dist.c hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI 2018-01-11 13:25:40 +00:00
arm_gicv3_its_common.c hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI 2018-01-11 13:25:40 +00:00
arm_gicv3_its_kvm.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
arm_gicv3_kvm.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
arm_gicv3_redist.c hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI 2018-01-11 13:25:40 +00:00
armv7m_nvic.c hw/intc/armv7m_nvic: Implement cache ID registers 2018-02-15 18:29:49 +00:00
aspeed_vic.c hw: Clean up includes 2016-06-07 18:19:23 +03:00
bcm2835_ic.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
bcm2836_control.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
etraxfs_pic.c qdev: Replace cannot_instantiate_with_device_add_yet with !user_creatable 2017-05-17 10:37:00 -03:00
exynos4210_combiner.c hw/intc: QOM'ify exynos4210_combiner.c 2016-05-12 13:22:24 +01:00
exynos4210_gic.c hw/intc/exynos4210_gic: Constify array of combiner interrupts 2017-06-13 14:56:58 +01:00
gic_internal.h arm: gic: Remove references to NVIC 2017-02-28 12:08:17 +00:00
gicv3_internal.h target-arm: Add GICv3CPUState in CPUARMState struct 2017-02-28 17:10:00 +00:00
grlib_irqmp.c sparc/leon3 irqmp: fix IRQ software ack 2018-01-24 19:19:50 +00:00
heathrow_pic.c hw/intc: Clean up includes 2016-01-29 15:07:24 +00:00
i8259.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
i8259_common.c i8259: move TYPE_INTERRUPT_STATS_PROVIDER upper 2017-12-21 09:30:32 +01:00
imx_avic.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
imx_gpcv2.c i.MX: Add code to emulate GPCv2 IP block 2018-02-09 10:40:30 +00:00
intc.c intc: add an interface to gather statistics/informations on interrupt controllers 2016-10-04 10:00:25 +02:00
ioapic.c ioapic/tracing: Remove last DPRINTFs 2017-11-14 14:31:33 +01:00
ioapic_common.c migration: pre_save return int 2017-09-27 11:35:59 +01:00
lm32_pic.c misc: drop old i386 dependency 2017-12-18 17:07:03 +03:00
Makefile.objs i.MX: Add code to emulate GPCv2 IP block 2018-02-09 10:40:30 +00:00
mips_gic.c hw/mips_gic: Update pin state on mask changes 2017-02-21 22:24:58 +00:00
nios2_iic.c qdev: Replace cannot_instantiate_with_device_add_yet with !user_creatable 2017-05-17 10:37:00 -03:00
omap_intc.c Replace all occurances of __FUNCTION__ with __func__ 2018-01-22 09:46:18 +01:00
ompic.c openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) 2017-10-21 06:35:47 +09:00
openpic.c openpic: debug w/ info_report() 2017-12-15 09:49:24 +11:00
openpic_kvm.c memory: Switch memory from using AddressSpace to FlatView 2017-09-21 23:19:37 +02:00
pl190.c hw: explicitly include qemu/log.h 2016-05-19 16:42:29 +02:00
puv3_intc.c unicore: Clean up includes 2016-01-29 15:07:22 +00:00
realview_gic.c include/qemu/osdep.h: Don't include qapi/error.h 2016-03-22 22:20:15 +01:00
s390_flic.c s390x/flic: cache the common flic class in a central function 2018-02-09 09:37:13 +01:00
s390_flic_kvm.c s390x/kvm: cache the kvm flic in a central function 2018-02-09 09:37:13 +01:00
sh_intc.c hw: explicitly include qemu-common.h and cpu.h 2016-03-22 22:20:17 +01:00
slavio_intctl.c sun4m: remove include/hw/sparc/sun4m.h and all references to it 2018-01-09 21:48:20 +00:00
trace-events target/arm: Split "get pending exception info" from "acknowledge it" 2018-02-09 10:40:27 +00:00
vgic_common.h intc/gic: Extract some reusable vGIC code 2015-09-24 01:29:36 +01:00
xics.c spapr: introduce a spapr_qirq() helper 2017-12-15 09:49:24 +11:00
xics_kvm.c xics/kvm: synchonize state before 'info pic' 2017-11-14 11:12:42 +11:00
xics_pnv.c Include qapi/error.h exactly where needed 2018-02-09 13:50:17 +01:00
xics_spapr.c Include qapi/error.h exactly where needed 2018-02-09 13:50:17 +01:00
xilinx_intc.c hw/intc: Clean up includes 2016-01-29 15:07:24 +00:00
xlnx-pmu-iomod-intc.c xlnx-pmu-iomod-intc: Add the PMU Interrupt controller 2018-01-26 11:09:09 +01:00
xlnx-zynqmp-ipi.c xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device 2018-01-26 11:09:09 +01:00