This is the implementation of the DPDMA. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> Message-id: 1465833014-21982-8-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
787 lines
26 KiB
C
787 lines
26 KiB
C
/*
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* xlnx_dpdma.c
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*
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* Copyright (C) 2015 : GreenSocs Ltd
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* http://www.greensocs.com/ , email: info@greensocs.com
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*
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* Developed by :
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* Frederic Konrad <fred.konrad@greensocs.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/dma/xlnx_dpdma.h"
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#ifndef DEBUG_DPDMA
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#define DEBUG_DPDMA 0
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#endif
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_DPDMA) { \
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qemu_log("xlnx_dpdma: " fmt , ## __VA_ARGS__); \
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} \
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} while (0);
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/*
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* Registers offset for DPDMA.
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*/
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#define DPDMA_ERR_CTRL (0x0000)
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#define DPDMA_ISR (0x0004 >> 2)
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#define DPDMA_IMR (0x0008 >> 2)
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#define DPDMA_IEN (0x000C >> 2)
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#define DPDMA_IDS (0x0010 >> 2)
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#define DPDMA_EISR (0x0014 >> 2)
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#define DPDMA_EIMR (0x0018 >> 2)
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#define DPDMA_EIEN (0x001C >> 2)
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#define DPDMA_EIDS (0x0020 >> 2)
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#define DPDMA_CNTL (0x0100 >> 2)
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#define DPDMA_GBL (0x0104 >> 2)
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#define DPDMA_GBL_TRG_CH(n) (1 << n)
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#define DPDMA_GBL_RTRG_CH(n) (1 << 6 << n)
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#define DPDMA_ALC0_CNTL (0x0108 >> 2)
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#define DPDMA_ALC0_STATUS (0x010C >> 2)
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#define DPDMA_ALC0_MAX (0x0110 >> 2)
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#define DPDMA_ALC0_MIN (0x0114 >> 2)
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#define DPDMA_ALC0_ACC (0x0118 >> 2)
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#define DPDMA_ALC0_ACC_TRAN (0x011C >> 2)
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#define DPDMA_ALC1_CNTL (0x0120 >> 2)
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#define DPDMA_ALC1_STATUS (0x0124 >> 2)
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#define DPDMA_ALC1_MAX (0x0128 >> 2)
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#define DPDMA_ALC1_MIN (0x012C >> 2)
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#define DPDMA_ALC1_ACC (0x0130 >> 2)
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#define DPDMA_ALC1_ACC_TRAN (0x0134 >> 2)
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#define DPDMA_DSCR_STRT_ADDRE_CH(n) ((0x0200 + n * 0x100) >> 2)
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#define DPDMA_DSCR_STRT_ADDR_CH(n) ((0x0204 + n * 0x100) >> 2)
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#define DPDMA_DSCR_NEXT_ADDRE_CH(n) ((0x0208 + n * 0x100) >> 2)
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#define DPDMA_DSCR_NEXT_ADDR_CH(n) ((0x020C + n * 0x100) >> 2)
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#define DPDMA_PYLD_CUR_ADDRE_CH(n) ((0x0210 + n * 0x100) >> 2)
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#define DPDMA_PYLD_CUR_ADDR_CH(n) ((0x0214 + n * 0x100) >> 2)
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#define DPDMA_CNTL_CH(n) ((0x0218 + n * 0x100) >> 2)
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#define DPDMA_CNTL_CH_EN (1)
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#define DPDMA_CNTL_CH_PAUSED (1 << 1)
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#define DPDMA_STATUS_CH(n) ((0x021C + n * 0x100) >> 2)
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#define DPDMA_STATUS_BURST_TYPE (1 << 4)
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#define DPDMA_STATUS_MODE (1 << 5)
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#define DPDMA_STATUS_EN_CRC (1 << 6)
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#define DPDMA_STATUS_LAST_DSCR (1 << 7)
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#define DPDMA_STATUS_LDSCR_FRAME (1 << 8)
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#define DPDMA_STATUS_IGNR_DONE (1 << 9)
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#define DPDMA_STATUS_DSCR_DONE (1 << 10)
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#define DPDMA_STATUS_EN_DSCR_UP (1 << 11)
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#define DPDMA_STATUS_EN_DSCR_INTR (1 << 12)
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#define DPDMA_STATUS_PREAMBLE_OFF (13)
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#define DPDMA_VDO_CH(n) ((0x0220 + n * 0x100) >> 2)
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#define DPDMA_PYLD_SZ_CH(n) ((0x0224 + n * 0x100) >> 2)
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#define DPDMA_DSCR_ID_CH(n) ((0x0228 + n * 0x100) >> 2)
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/*
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* Descriptor control field.
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*/
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#define CONTROL_PREAMBLE_VALUE 0xA5
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#define DSCR_CTRL_PREAMBLE 0xFF
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#define DSCR_CTRL_EN_DSCR_DONE_INTR (1 << 8)
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#define DSCR_CTRL_EN_DSCR_UPDATE (1 << 9)
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#define DSCR_CTRL_IGNORE_DONE (1 << 10)
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#define DSCR_CTRL_AXI_BURST_TYPE (1 << 11)
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#define DSCR_CTRL_AXCACHE (0x0F << 12)
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#define DSCR_CTRL_AXPROT (0x2 << 16)
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#define DSCR_CTRL_DESCRIPTOR_MODE (1 << 18)
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#define DSCR_CTRL_LAST_DESCRIPTOR (1 << 19)
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#define DSCR_CTRL_ENABLE_CRC (1 << 20)
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#define DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME (1 << 21)
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/*
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* Descriptor timestamp field.
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*/
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#define STATUS_DONE (1 << 31)
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#define DPDMA_FRAG_MAX_SZ (4096)
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enum DPDMABurstType {
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DPDMA_INCR = 0,
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DPDMA_FIXED = 1
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};
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enum DPDMAMode {
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DPDMA_CONTIGOUS = 0,
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DPDMA_FRAGMENTED = 1
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};
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struct DPDMADescriptor {
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uint32_t control;
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uint32_t descriptor_id;
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/* transfer size in byte. */
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uint32_t xfer_size;
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uint32_t line_size_stride;
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uint32_t timestamp_lsb;
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uint32_t timestamp_msb;
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/* contains extension for both descriptor and source. */
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uint32_t address_extension;
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uint32_t next_descriptor;
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uint32_t source_address;
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uint32_t address_extension_23;
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uint32_t address_extension_45;
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uint32_t source_address2;
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uint32_t source_address3;
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uint32_t source_address4;
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uint32_t source_address5;
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uint32_t crc;
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};
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typedef enum DPDMABurstType DPDMABurstType;
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typedef enum DPDMAMode DPDMAMode;
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typedef struct DPDMADescriptor DPDMADescriptor;
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static bool xlnx_dpdma_desc_is_last(DPDMADescriptor *desc)
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{
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return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0);
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}
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static bool xlnx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
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{
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return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME) != 0);
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}
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static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
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uint8_t frag)
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{
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uint64_t addr = 0;
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assert(frag < 5);
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switch (frag) {
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case 0:
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addr = desc->source_address
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+ (extract32(desc->address_extension, 16, 12) << 20);
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break;
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case 1:
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addr = desc->source_address2
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+ (extract32(desc->address_extension_23, 0, 12) << 8);
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break;
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case 2:
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addr = desc->source_address3
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+ (extract32(desc->address_extension_23, 16, 12) << 20);
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break;
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case 3:
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addr = desc->source_address4
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+ (extract32(desc->address_extension_45, 0, 12) << 8);
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break;
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case 4:
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addr = desc->source_address5
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+ (extract32(desc->address_extension_45, 16, 12) << 20);
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break;
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default:
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addr = 0;
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break;
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}
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return addr;
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}
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static uint32_t xlnx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
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{
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return desc->xfer_size;
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}
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static uint32_t xlnx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
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{
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return extract32(desc->line_size_stride, 0, 18);
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}
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static uint32_t xlnx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
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{
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return extract32(desc->line_size_stride, 18, 14) * 16;
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}
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static inline bool xlnx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_ENABLE_CRC) != 0;
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}
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static inline bool xlnx_dpdma_desc_check_crc(DPDMADescriptor *desc)
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{
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uint32_t *p = (uint32_t *)desc;
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uint32_t crc = 0;
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uint8_t i;
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/*
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* CRC is calculated on the whole descriptor except the last 32bits word
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* using 32bits addition.
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*/
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for (i = 0; i < 15; i++) {
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crc += p[i];
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}
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return crc == desc->crc;
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}
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static inline bool xlnx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_EN_DSCR_DONE_INTR) != 0;
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}
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static inline bool xlnx_dpdma_desc_is_valid(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_PREAMBLE) == CONTROL_PREAMBLE_VALUE;
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}
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static inline bool xlnx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_DESCRIPTOR_MODE) == 0;
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}
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static inline bool xlnx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0;
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}
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static inline void xlnx_dpdma_desc_set_done(DPDMADescriptor *desc)
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{
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desc->timestamp_msb |= STATUS_DONE;
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}
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static inline bool xlnx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
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{
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return (desc->timestamp_msb & STATUS_DONE) != 0;
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}
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static inline bool xlnx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
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{
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return (desc->control & DSCR_CTRL_IGNORE_DONE) != 0;
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}
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static const VMStateDescription vmstate_xlnx_dpdma = {
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.name = TYPE_XLNX_DPDMA,
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(registers, XlnxDPDMAState,
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XLNX_DPDMA_REG_ARRAY_SIZE),
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VMSTATE_BOOL_ARRAY(operation_finished, XlnxDPDMAState, 6),
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VMSTATE_END_OF_LIST()
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}
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};
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static void xlnx_dpdma_update_irq(XlnxDPDMAState *s)
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{
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bool flags;
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flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
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|| (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
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qemu_set_irq(s->irq, flags);
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}
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static uint64_t xlnx_dpdma_descriptor_start_address(XlnxDPDMAState *s,
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uint8_t channel)
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{
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return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16)
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+ s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)];
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}
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static uint64_t xlnx_dpdma_descriptor_next_address(XlnxDPDMAState *s,
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uint8_t channel)
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{
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return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32)
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+ s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)];
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}
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static bool xlnx_dpdma_is_channel_enabled(XlnxDPDMAState *s,
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uint8_t channel)
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{
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return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0;
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}
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static bool xlnx_dpdma_is_channel_paused(XlnxDPDMAState *s,
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uint8_t channel)
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{
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return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0;
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}
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static inline bool xlnx_dpdma_is_channel_retriggered(XlnxDPDMAState *s,
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uint8_t channel)
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{
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/* Clear the retriggered bit after reading it. */
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bool channel_is_retriggered = s->registers[DPDMA_GBL]
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& DPDMA_GBL_RTRG_CH(channel);
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s->registers[DPDMA_GBL] &= ~DPDMA_GBL_RTRG_CH(channel);
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return channel_is_retriggered;
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}
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static inline bool xlnx_dpdma_is_channel_triggered(XlnxDPDMAState *s,
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uint8_t channel)
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{
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return s->registers[DPDMA_GBL] & DPDMA_GBL_TRG_CH(channel);
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}
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static void xlnx_dpdma_update_desc_info(XlnxDPDMAState *s, uint8_t channel,
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DPDMADescriptor *desc)
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{
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s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] =
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extract32(desc->address_extension, 0, 16);
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s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = desc->next_descriptor;
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s->registers[DPDMA_PYLD_CUR_ADDRE_CH(channel)] =
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extract32(desc->address_extension, 16, 16);
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s->registers[DPDMA_PYLD_CUR_ADDR_CH(channel)] = desc->source_address;
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s->registers[DPDMA_VDO_CH(channel)] =
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extract32(desc->line_size_stride, 18, 14)
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+ (extract32(desc->line_size_stride, 0, 18)
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<< 14);
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s->registers[DPDMA_PYLD_SZ_CH(channel)] = desc->xfer_size;
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s->registers[DPDMA_DSCR_ID_CH(channel)] = desc->descriptor_id;
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/* Compute the status register with the descriptor information. */
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s->registers[DPDMA_STATUS_CH(channel)] =
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extract32(desc->control, 0, 8) << 13;
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if ((desc->control & DSCR_CTRL_EN_DSCR_DONE_INTR) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_INTR;
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}
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if ((desc->control & DSCR_CTRL_EN_DSCR_UPDATE) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_UP;
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}
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if ((desc->timestamp_msb & STATUS_DONE) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_DSCR_DONE;
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}
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if ((desc->control & DSCR_CTRL_IGNORE_DONE) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_IGNR_DONE;
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}
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if ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LDSCR_FRAME;
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}
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if ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LAST_DSCR;
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}
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if ((desc->control & DSCR_CTRL_ENABLE_CRC) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_CRC;
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}
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if ((desc->control & DSCR_CTRL_DESCRIPTOR_MODE) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_MODE;
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}
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if ((desc->control & DSCR_CTRL_AXI_BURST_TYPE) != 0) {
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s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_BURST_TYPE;
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}
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}
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static void xlnx_dpdma_dump_descriptor(DPDMADescriptor *desc)
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{
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if (DEBUG_DPDMA) {
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qemu_log("DUMP DESCRIPTOR:\n");
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qemu_hexdump((char *)desc, stdout, "", sizeof(DPDMADescriptor));
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}
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}
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static uint64_t xlnx_dpdma_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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XlnxDPDMAState *s = XLNX_DPDMA(opaque);
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DPRINTF("read @%" HWADDR_PRIx "\n", offset);
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offset = offset >> 2;
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switch (offset) {
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/*
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* Trying to read a write only register.
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*/
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case DPDMA_GBL:
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return 0;
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default:
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assert(offset <= (0xFFC >> 2));
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return s->registers[offset];
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}
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return 0;
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}
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static void xlnx_dpdma_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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XlnxDPDMAState *s = XLNX_DPDMA(opaque);
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DPRINTF("write @%" HWADDR_PRIx " = %" PRIx64 "\n", offset, value);
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offset = offset >> 2;
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switch (offset) {
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case DPDMA_ISR:
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s->registers[DPDMA_ISR] &= ~value;
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xlnx_dpdma_update_irq(s);
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break;
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case DPDMA_IEN:
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s->registers[DPDMA_IMR] &= ~value;
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break;
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case DPDMA_IDS:
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s->registers[DPDMA_IMR] |= value;
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break;
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case DPDMA_EISR:
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s->registers[DPDMA_EISR] &= ~value;
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xlnx_dpdma_update_irq(s);
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break;
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case DPDMA_EIEN:
|
|
s->registers[DPDMA_EIMR] &= ~value;
|
|
break;
|
|
case DPDMA_EIDS:
|
|
s->registers[DPDMA_EIMR] |= value;
|
|
break;
|
|
case DPDMA_IMR:
|
|
case DPDMA_EIMR:
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(0):
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(1):
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(2):
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(3):
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(4):
|
|
case DPDMA_DSCR_NEXT_ADDRE_CH(5):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(0):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(1):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(2):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(3):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(4):
|
|
case DPDMA_DSCR_NEXT_ADDR_CH(5):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(0):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(1):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(2):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(3):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(4):
|
|
case DPDMA_PYLD_CUR_ADDRE_CH(5):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(0):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(1):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(2):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(3):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(4):
|
|
case DPDMA_PYLD_CUR_ADDR_CH(5):
|
|
case DPDMA_STATUS_CH(0):
|
|
case DPDMA_STATUS_CH(1):
|
|
case DPDMA_STATUS_CH(2):
|
|
case DPDMA_STATUS_CH(3):
|
|
case DPDMA_STATUS_CH(4):
|
|
case DPDMA_STATUS_CH(5):
|
|
case DPDMA_VDO_CH(0):
|
|
case DPDMA_VDO_CH(1):
|
|
case DPDMA_VDO_CH(2):
|
|
case DPDMA_VDO_CH(3):
|
|
case DPDMA_VDO_CH(4):
|
|
case DPDMA_VDO_CH(5):
|
|
case DPDMA_PYLD_SZ_CH(0):
|
|
case DPDMA_PYLD_SZ_CH(1):
|
|
case DPDMA_PYLD_SZ_CH(2):
|
|
case DPDMA_PYLD_SZ_CH(3):
|
|
case DPDMA_PYLD_SZ_CH(4):
|
|
case DPDMA_PYLD_SZ_CH(5):
|
|
case DPDMA_DSCR_ID_CH(0):
|
|
case DPDMA_DSCR_ID_CH(1):
|
|
case DPDMA_DSCR_ID_CH(2):
|
|
case DPDMA_DSCR_ID_CH(3):
|
|
case DPDMA_DSCR_ID_CH(4):
|
|
case DPDMA_DSCR_ID_CH(5):
|
|
/*
|
|
* Trying to write to a read only register..
|
|
*/
|
|
break;
|
|
case DPDMA_GBL:
|
|
/*
|
|
* This is a write only register so it's read as zero in the read
|
|
* callback.
|
|
* We store the value anyway so we can know if the channel is
|
|
* enabled.
|
|
*/
|
|
s->registers[offset] |= value & 0x00000FFF;
|
|
break;
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(0):
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(1):
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(2):
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(3):
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(4):
|
|
case DPDMA_DSCR_STRT_ADDRE_CH(5):
|
|
value &= 0x0000FFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(0):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(0);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(1):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(1);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(2):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(2);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(3):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(3);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(4):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(4);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
case DPDMA_CNTL_CH(5):
|
|
s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(5);
|
|
value &= 0x3FFFFFFF;
|
|
s->registers[offset] = value;
|
|
break;
|
|
default:
|
|
assert(offset <= (0xFFC >> 2));
|
|
s->registers[offset] = value;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps dma_ops = {
|
|
.read = xlnx_dpdma_read,
|
|
.write = xlnx_dpdma_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static void xlnx_dpdma_init(Object *obj)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
XlnxDPDMAState *s = XLNX_DPDMA(obj);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &dma_ops, s,
|
|
TYPE_XLNX_DPDMA, 0x1000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
}
|
|
|
|
static void xlnx_dpdma_reset(DeviceState *dev)
|
|
{
|
|
XlnxDPDMAState *s = XLNX_DPDMA(dev);
|
|
size_t i;
|
|
|
|
memset(s->registers, 0, sizeof(s->registers));
|
|
s->registers[DPDMA_IMR] = 0x07FFFFFF;
|
|
s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
|
|
s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
|
|
s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
s->data[i] = NULL;
|
|
s->operation_finished[i] = true;
|
|
}
|
|
}
|
|
|
|
static void xlnx_dpdma_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->vmsd = &vmstate_xlnx_dpdma;
|
|
dc->reset = xlnx_dpdma_reset;
|
|
}
|
|
|
|
static const TypeInfo xlnx_dpdma_info = {
|
|
.name = TYPE_XLNX_DPDMA,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(XlnxDPDMAState),
|
|
.instance_init = xlnx_dpdma_init,
|
|
.class_init = xlnx_dpdma_class_init,
|
|
};
|
|
|
|
static void xlnx_dpdma_register_types(void)
|
|
{
|
|
type_register_static(&xlnx_dpdma_info);
|
|
}
|
|
|
|
size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, uint8_t channel,
|
|
bool one_desc)
|
|
{
|
|
uint64_t desc_addr;
|
|
uint64_t source_addr[6];
|
|
DPDMADescriptor desc;
|
|
bool done = false;
|
|
size_t ptr = 0;
|
|
|
|
assert(channel <= 5);
|
|
|
|
DPRINTF("start dpdma channel 0x%" PRIX8 "\n", channel);
|
|
|
|
if (!xlnx_dpdma_is_channel_triggered(s, channel)) {
|
|
DPRINTF("Channel isn't triggered..\n");
|
|
return 0;
|
|
}
|
|
|
|
if (!xlnx_dpdma_is_channel_enabled(s, channel)) {
|
|
DPRINTF("Channel isn't enabled..\n");
|
|
return 0;
|
|
}
|
|
|
|
if (xlnx_dpdma_is_channel_paused(s, channel)) {
|
|
DPRINTF("Channel is paused..\n");
|
|
return 0;
|
|
}
|
|
|
|
do {
|
|
if ((s->operation_finished[channel])
|
|
|| xlnx_dpdma_is_channel_retriggered(s, channel)) {
|
|
desc_addr = xlnx_dpdma_descriptor_start_address(s, channel);
|
|
s->operation_finished[channel] = false;
|
|
} else {
|
|
desc_addr = xlnx_dpdma_descriptor_next_address(s, channel);
|
|
}
|
|
|
|
if (dma_memory_read(&address_space_memory, desc_addr, &desc,
|
|
sizeof(DPDMADescriptor))) {
|
|
s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
s->operation_finished[channel] = true;
|
|
DPRINTF("Can't get the descriptor.\n");
|
|
break;
|
|
}
|
|
|
|
xlnx_dpdma_update_desc_info(s, channel, &desc);
|
|
|
|
#ifdef DEBUG_DPDMA
|
|
xlnx_dpdma_dump_descriptor(&desc);
|
|
#endif
|
|
|
|
DPRINTF("location of the descriptor: %" PRIx64 "\n", desc_addr);
|
|
if (!xlnx_dpdma_desc_is_valid(&desc)) {
|
|
s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
s->operation_finished[channel] = true;
|
|
DPRINTF("Invalid descriptor..\n");
|
|
break;
|
|
}
|
|
|
|
if (xlnx_dpdma_desc_crc_enabled(&desc)
|
|
&& !xlnx_dpdma_desc_check_crc(&desc)) {
|
|
s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
s->operation_finished[channel] = true;
|
|
DPRINTF("Bad CRC for descriptor..\n");
|
|
break;
|
|
}
|
|
|
|
if (xlnx_dpdma_desc_is_already_done(&desc)
|
|
&& !xlnx_dpdma_desc_ignore_done_bit(&desc)) {
|
|
/* We are trying to process an already processed descriptor. */
|
|
s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
s->operation_finished[channel] = true;
|
|
DPRINTF("Already processed descriptor..\n");
|
|
break;
|
|
}
|
|
|
|
done = xlnx_dpdma_desc_is_last(&desc)
|
|
|| xlnx_dpdma_desc_is_last_of_frame(&desc);
|
|
|
|
s->operation_finished[channel] = done;
|
|
if (s->data[channel]) {
|
|
int64_t transfer_len = xlnx_dpdma_desc_get_transfer_size(&desc);
|
|
uint32_t line_size = xlnx_dpdma_desc_get_line_size(&desc);
|
|
uint32_t line_stride = xlnx_dpdma_desc_get_line_stride(&desc);
|
|
if (xlnx_dpdma_desc_is_contiguous(&desc)) {
|
|
source_addr[0] = xlnx_dpdma_desc_get_source_address(&desc, 0);
|
|
while (transfer_len != 0) {
|
|
if (dma_memory_read(&address_space_memory,
|
|
source_addr[0],
|
|
&s->data[channel][ptr],
|
|
line_size)) {
|
|
s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
DPRINTF("Can't get data.\n");
|
|
break;
|
|
}
|
|
ptr += line_size;
|
|
transfer_len -= line_size;
|
|
source_addr[0] += line_stride;
|
|
}
|
|
} else {
|
|
DPRINTF("Source address:\n");
|
|
int frag;
|
|
for (frag = 0; frag < 5; frag++) {
|
|
source_addr[frag] =
|
|
xlnx_dpdma_desc_get_source_address(&desc, frag);
|
|
DPRINTF("Fragment %u: %" PRIx64 "\n", frag + 1,
|
|
source_addr[frag]);
|
|
}
|
|
|
|
frag = 0;
|
|
while ((transfer_len < 0) && (frag < 5)) {
|
|
size_t fragment_len = DPDMA_FRAG_MAX_SZ
|
|
- (source_addr[frag] % DPDMA_FRAG_MAX_SZ);
|
|
|
|
if (dma_memory_read(&address_space_memory,
|
|
source_addr[frag],
|
|
&(s->data[channel][ptr]),
|
|
fragment_len)) {
|
|
s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
DPRINTF("Can't get data.\n");
|
|
break;
|
|
}
|
|
ptr += fragment_len;
|
|
transfer_len -= fragment_len;
|
|
frag += 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (xlnx_dpdma_desc_update_enabled(&desc)) {
|
|
/* The descriptor need to be updated when it's completed. */
|
|
DPRINTF("update the descriptor with the done flag set.\n");
|
|
xlnx_dpdma_desc_set_done(&desc);
|
|
dma_memory_write(&address_space_memory, desc_addr, &desc,
|
|
sizeof(DPDMADescriptor));
|
|
}
|
|
|
|
if (xlnx_dpdma_desc_completion_interrupt(&desc)) {
|
|
DPRINTF("completion interrupt enabled!\n");
|
|
s->registers[DPDMA_ISR] |= (1 << channel);
|
|
xlnx_dpdma_update_irq(s);
|
|
}
|
|
|
|
} while (!done && !one_desc);
|
|
|
|
return ptr;
|
|
}
|
|
|
|
void xlnx_dpdma_set_host_data_location(XlnxDPDMAState *s, uint8_t channel,
|
|
void *p)
|
|
{
|
|
if (!s) {
|
|
qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
|
|
" instance\n");
|
|
return;
|
|
}
|
|
|
|
assert(channel <= 5);
|
|
s->data[channel] = p;
|
|
}
|
|
|
|
void xlnx_dpdma_trigger_vsync_irq(XlnxDPDMAState *s)
|
|
{
|
|
s->registers[DPDMA_ISR] |= (1 << 27);
|
|
xlnx_dpdma_update_irq(s);
|
|
}
|
|
|
|
type_init(xlnx_dpdma_register_types)
|