The AST2500 datasheet says: I2CD10 Interrupt Status Register bit 2 Receive Done Interrupt status S/W needs to clear this status bit to allow next data receiving The Rx interrupt done interrupt status bit needs to be cleared explicitly before the next byte can be received, and must therefore not be auto-cleared. Also, receiving the next byte must be delayed until the bit has been cleared. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180914063506.20815-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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aspeed_i2c.c | ||
bitbang_i2c.c | ||
bitbang_i2c.h | ||
core.c | ||
exynos4210_i2c.c | ||
i2c-ddc.c | ||
imx_i2c.c | ||
Makefile.objs | ||
omap_i2c.c | ||
pm_smbus.c | ||
ppc4xx_i2c.c | ||
smbus.c | ||
smbus_eeprom.c | ||
smbus_ich9.c | ||
trace-events | ||
versatile_i2c.c |