qemu-patch-raspberry4/target
Philipp Tomsich 45d1749c1c target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
	bseti	a2, zero, 63
	addi	a2, a2, 392
	clzw    a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).

Fix this by changing the implementation to:
 1. shift the original register up by 32
 2. performs a target-length (64bit) clz
 3. return 32 if no bits are set

Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed).  Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-07 08:32:47 +10:00
..
alpha hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
arm tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
avr include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
cris include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
hexagon target/hexagon: Use tcg_constant_* 2021-10-06 10:29:56 -05:00
hppa hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
i386 tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
m68k tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
microblaze hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
mips tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
nios2 hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
openrisc include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
ppc target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l] 2021-09-30 12:26:06 +10:00
riscv target/riscv: clwz must ignore high bits (use shift-left & changed logic) 2021-10-07 08:32:47 +10:00
rx include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
s390x tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
sh4 target/sh4: Use lookup_symbol in sh4_tr_disas_log 2021-10-04 09:47:26 +02:00
sparc tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
tricore include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
xtensa target/xtensa: list cores in a text file 2021-10-05 13:10:29 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00