The QTests perform five tests on the Xilinx ZynqMP CAN controller: Tests the CAN controller in loopback, sleep and snoop mode. Tests filtering of incoming CAN messages. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
361 lines
13 KiB
C
361 lines
13 KiB
C
/*
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* QTests for the Xilinx ZynqMP CAN controller.
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*
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* Copyright (c) 2020 Xilinx Inc.
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*
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* Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "libqos/libqtest.h"
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/* Base address. */
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#define CAN0_BASE_ADDR 0xFF060000
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#define CAN1_BASE_ADDR 0xFF070000
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/* Register addresses. */
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#define R_SRR_OFFSET 0x00
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#define R_MSR_OFFSET 0x04
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#define R_SR_OFFSET 0x18
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#define R_ISR_OFFSET 0x1C
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#define R_ICR_OFFSET 0x24
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#define R_TXID_OFFSET 0x30
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#define R_TXDLC_OFFSET 0x34
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#define R_TXDATA1_OFFSET 0x38
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#define R_TXDATA2_OFFSET 0x3C
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#define R_RXID_OFFSET 0x50
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#define R_RXDLC_OFFSET 0x54
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#define R_RXDATA1_OFFSET 0x58
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#define R_RXDATA2_OFFSET 0x5C
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#define R_AFR 0x60
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#define R_AFMR1 0x64
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#define R_AFIR1 0x68
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#define R_AFMR2 0x6C
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#define R_AFIR2 0x70
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#define R_AFMR3 0x74
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#define R_AFIR3 0x78
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#define R_AFMR4 0x7C
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#define R_AFIR4 0x80
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/* CAN modes. */
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#define CONFIG_MODE 0x00
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#define NORMAL_MODE 0x00
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#define LOOPBACK_MODE 0x02
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#define SNOOP_MODE 0x04
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#define SLEEP_MODE 0x01
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#define ENABLE_CAN (1 << 1)
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#define STATUS_NORMAL_MODE (1 << 3)
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#define STATUS_LOOPBACK_MODE (1 << 1)
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#define STATUS_SNOOP_MODE (1 << 12)
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#define STATUS_SLEEP_MODE (1 << 2)
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#define ISR_TXOK (1 << 1)
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#define ISR_RXOK (1 << 4)
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static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
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uint8_t can_timestamp)
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{
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uint16_t size = 0;
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uint8_t len = 4;
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while (size < len) {
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if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) {
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g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
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} else {
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g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
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}
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size++;
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}
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}
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static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
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{
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uint32_t int_status;
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/* Read the interrupt on CAN rx. */
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int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
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g_assert_cmpint(int_status, ==, ISR_RXOK);
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/* Read the RX register data for CAN. */
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buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
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buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
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buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
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buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
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/* Clear the RX interrupt. */
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qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
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}
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static void send_data(QTestState *qts, uint64_t can_base_addr,
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const uint32_t *buf_tx)
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{
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uint32_t int_status;
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/* Write the TX register data for CAN. */
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qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
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qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
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qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
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qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
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/* Read the interrupt on CAN for tx. */
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int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
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g_assert_cmpint(int_status, ==, ISR_TXOK);
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/* Clear the interrupt for tx. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
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}
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/*
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* This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
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* initiate the data transfer to can-bus, CAN1 receives the data. Test compares
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* the data sent from CAN0 with received on CAN1.
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*/
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static void test_can_bus(void)
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{
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const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
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uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
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uint32_t status = 0;
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uint8_t can_timestamp = 1;
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QTestState *qts = qtest_init("-machine xlnx-zcu102"
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" -object can-bus,id=canbus0"
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" -machine xlnx-zcu102.canbus0=canbus0"
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" -machine xlnx-zcu102.canbus1=canbus0"
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);
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/* Configure the CAN0 and CAN1. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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/* Check here if CAN0 and CAN1 are in normal mode. */
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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send_data(qts, CAN0_BASE_ADDR, buf_tx);
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read_data(qts, CAN1_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
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qtest_quit(qts);
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}
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/*
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* This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
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* each CAN0 and CAN1 are compared with RX register data for respective CAN.
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*/
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static void test_can_loopback(void)
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{
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uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
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uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
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uint32_t status = 0;
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QTestState *qts = qtest_init("-machine xlnx-zcu102"
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" -object can-bus,id=canbus0"
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" -machine xlnx-zcu102.canbus0=canbus0"
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" -machine xlnx-zcu102.canbus1=canbus0"
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);
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/* Configure the CAN0 in loopback mode. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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/* Check here if CAN0 is set in loopback mode. */
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
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send_data(qts, CAN0_BASE_ADDR, buf_tx);
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read_data(qts, CAN0_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, 0);
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/* Configure the CAN1 in loopback mode. */
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
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qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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/* Check here if CAN1 is set in loopback mode. */
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status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
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send_data(qts, CAN1_BASE_ADDR, buf_tx);
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read_data(qts, CAN1_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, 0);
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qtest_quit(qts);
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}
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/*
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* Enable filters for CAN1. This will filter incoming messages with ID. In this
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* test message will pass through filter 2.
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*/
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static void test_can_filter(void)
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{
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uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
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uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
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uint32_t status = 0;
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uint8_t can_timestamp = 1;
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QTestState *qts = qtest_init("-machine xlnx-zcu102"
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" -object can-bus,id=canbus0"
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" -machine xlnx-zcu102.canbus0=canbus0"
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" -machine xlnx-zcu102.canbus1=canbus0"
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);
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/* Configure the CAN0 and CAN1. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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/* Check here if CAN0 and CAN1 are in normal mode. */
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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/* Set filter for CAN1 for incoming messages. */
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
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qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
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send_data(qts, CAN0_BASE_ADDR, buf_tx);
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read_data(qts, CAN1_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
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qtest_quit(qts);
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}
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/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
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static void test_can_sleepmode(void)
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{
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uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
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uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
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uint32_t status = 0;
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uint8_t can_timestamp = 1;
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QTestState *qts = qtest_init("-machine xlnx-zcu102"
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" -object can-bus,id=canbus0"
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" -machine xlnx-zcu102.canbus0=canbus0"
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" -machine xlnx-zcu102.canbus1=canbus0"
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);
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/* Configure the CAN0. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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/* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
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status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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send_data(qts, CAN1_BASE_ADDR, buf_tx);
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/*
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* Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
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* Check the CAN0 status now. It should exit the sleep mode and receive the
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* incoming data.
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*/
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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read_data(qts, CAN0_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
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qtest_quit(qts);
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}
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/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
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static void test_can_snoopmode(void)
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{
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uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
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uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
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uint32_t status = 0;
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uint8_t can_timestamp = 1;
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QTestState *qts = qtest_init("-machine xlnx-zcu102"
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" -object can-bus,id=canbus0"
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" -machine xlnx-zcu102.canbus0=canbus0"
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" -machine xlnx-zcu102.canbus1=canbus0"
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);
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/* Configure the CAN0. */
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
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qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
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qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
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/* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
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status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
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status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
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g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
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send_data(qts, CAN1_BASE_ADDR, buf_tx);
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read_data(qts, CAN0_BASE_ADDR, buf_rx);
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match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
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qtest_quit(qts);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/net/can/can_bus", test_can_bus);
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qtest_add_func("/net/can/can_loopback", test_can_loopback);
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qtest_add_func("/net/can/can_filter", test_can_filter);
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qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
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qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
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return g_test_run();
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}
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