qemu-patch-raspberry4/target/riscv
Jose Martins 487a99551a target/riscv: fix VS interrupts forwarding to HS
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are always globally enabled regardless of the setting of the global
yIE bit for the higher-privilege mode." and also "For purposes of
interrupt global enables, HS-mode is considered more privileged than
VS-mode, and VS-mode is considered more privileged than VU-mode". Also,
vs-level interrupts were not being taken into account unless V=1, but
should be unless delegated.

Finally, there is no need for a special case for to handle vs interrupts
as the current privilege level, the state of the global ie and of the
delegation registers should be enough to route all interrupts to the
appropriate privilege level in riscv_cpu_do_interrupt.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-2-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29 16:54:45 +10:00
..
insn_trans target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions 2021-10-28 14:39:23 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: Allow experimental J-ext to be turned on 2021-10-28 14:39:23 +10:00
cpu.h target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension 2021-10-28 14:39:23 +10:00
cpu_bits.h target/riscv: Add CSR defines for RISC-V PM extension 2021-10-28 14:39:23 +10:00
cpu_helper.c target/riscv: fix VS interrupts forwarding to HS 2021-10-29 16:54:45 +10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode 2021-10-28 14:39:23 +10:00
fpu_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00
gdbstub.c target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl 2021-10-22 07:47:51 +10:00
helper.h target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
insn16.decode target/riscv: Consolidate RV32/64 16-bit instructions 2021-05-11 20:02:07 +10:00
insn32.decode target/riscv: Remove RVB (replaced by Zb[abcs]) 2021-10-07 08:41:33 +10:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
machine.c target/riscv: Add J extension state description 2021-10-28 14:39:23 +10:00
meson.build target/riscv: rvb: generalized reverse 2021-06-08 09:59:45 +10:00
monitor.c target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl 2021-10-22 07:47:51 +10:00
op_helper.c target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
pmp.c target/riscv: pmp: Fix some typos 2021-07-15 08:56:00 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension 2021-10-28 14:39:23 +10:00
vector_helper.c target/riscv: Consolidate RV32/64 32-bit instructions 2021-05-11 20:02:07 +10:00